- FSI's systems are designed to use off-the-shelf tool prepared chemical mixtures or on-tool blending of dilute acids and additives.
- FSI's systems can be operated in both single pass and re-circulated modes.
- FSI's proprietary blending technology allows for very precise, repeatable control.
- FSI's spray cleaning systems maintain very low oxygen atmospheres that minimize unwanted metal etching or galvanic corrosion.
FSI International Releases ORION® Single Wafer Cleaning System
Innovative closed-chamber design enables critical path cleaning capabilities for ultra shallow junctions, high-k/metal gates and metal capping layers at 32nm and below.
MINNEAPOLIS (November 3, 2008) — FSI International, Inc. (Nasdaq: FSII) a leading supplier of wafer processing, cleaning and surface conditioning equipment for semiconductor manufacturing, announced today the release of its new ORION® Single Wafer Cleaning System.
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Controlling Dissolved Oxygen in Cleaning Processes
OTS (September 2008) -- Dissolved gases have long been known to have significant impact on wet cleaning processes. Dissolved oxygen in rinse water contributes to surface oxidation and watermark formation during wafer drying [1-2]. Dissolved gases can affect megasonics processes and are often controlled in order to optimize particle removal efficiency and prevent pattern damage [3]. In addition, dissolved CO2 is well-known to form carbonic acid, affecting the pH of liquid cleaning solutions. More recently, there is an increased concern about the effect of dissolved oxygen when cleaning surfaces with different metals exposed.
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Resist Removal Walks a Tightrope
At the 32 nm technology node and beyond, the most critical front-end-of-line (FEOL) cleans are during ultrashallow junction (USJ) formation, with an International Technology Roadmap for Semiconductors' (ITRS) target of 0.3 Å/clean of silicon loss. Meeting this challenge is most difficult for resist removal following high-dose implants.
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Increasing Demands Require New Look at Wafer Cleans
As device structures scale down, it is getting increasingly difficult to achieve low material loss while still removing particles. It is also getting more difficult to keep from damaging, attacking or otherwise modifying surrounding materials and structures — including doped silicon loss, changes in the k values of low-k dielectrics, metal gate corrosion, pattern collapse, and more.
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FSI Ships Single Wafer Cleaning Technology Selected by a Major Semiconductor Manufacturer for Development of 32nm BEOL Cleaning Processes
MINNEAPOLIS (May 13, 2008) -- FSI International, Inc. (Nasdaq: FSII), a leading manufacturer of wafer cleaning systems used in the fabrication of integrated circuits, announced today that it shipped its single wafer wet cleaning technology to a major semiconductor manufacturer for the development of back-end-of-line (BEOL) cleaning capability for 32nm IC manufacturing. After a thorough review of competitive alternatives, this customer determined that FSI’s technology best met its anticipated new requirements for 32nm device manufacturing. For the development program, FSI has shipped an evaluation ORION™ Single Wafer Cleaning Cluster.
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FSI International Introduces New Cleaning Processes for Advanced Technology Nodes New Processes Meet Customer Needs Well Ahead of ITRS Schedule
MINNEAPOLIS (June 30, 2005) -- FSI International, Inc. (Nasdaq: FSII) today announced new cleaning processes to meet the needs of leading IC makers well ahead of the International Technology Roadmap for Semiconductors (ITRS) guidelines for material loss. The ITRS calls for a maximum material loss per cleaning cycle of 0.4 angstrom at the 45nm technology node, while semiconductor manufacturers indicate their requirements are closer to 0.1 angstrom.
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FSI International Surface Preparation Products Gain Momentum in Asia
MINNEAPOLIS (September 14, 2004) -- FSI International, Inc. (Nasdaq: FSII) today announced that its surface preparation technology platforms are experiencing broad adoption in Asia, with sales to customers in the region accounting for nearly 40 percent of all orders in the first nine months of fiscal year 2004, up from 11 percent in the first nine months of fiscal 2003.
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FSI Joins Damascus™ Alliance to Integrate Cleaning into the Copper Dual Damascene Process
MINNEAPOLIS (May 11, 2004) -- FSI International, Inc. (Nasdaq: FSII) today announced that the company has signed a cooperative agreement with Novellus Systems, Inc. to join the Damascus Alliance™, a group of semiconductor equipment companies that collaborate on copper dual damascene process integration for advanced device manufacturing. FSI will install their fully automated 300-mm ZETA® Spray Cleaning System in the Novellus Customer Integration Center (CIC) in July. FSI’s expertise in the areas of post via etch, post trench etch, post barrier etch cleaning and other surface conditioning processes for use in copper and low k dual damascene processing compliments the expertise of other Alliance members.
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"Reducing Time in Batch Cleaning"
By: Jeffrey Butterbaugh, FSI International
Wafer cleaning represents up to 15% of the total process steps to build an advanced, 90-nm semiconductor device and is still mainly carried out in batch processes. Performance and throughput advantages are the main reasons for the persistence of batch processing in cleaning. However, concerns about cycle time are driving development of single wafer cleaning processes. Jeffery W. Butterbaugh of FSI International looks at alternatives for maintaining performance and throughput while realizing gains in productivity for cleaning processes.
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“Using Cost-Effective Dilute-Acid Chemicals to Perform Postetch Interconnect Cleans”
By: Hong-Seong Sohn, Samsung Electronics; and Jeffery W. Butterbaugh, Erik D. Olson, John Diedrick, and Nam-Pyo Lee
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“Non-Damaging Chemical Photoresist Strip Process for Copper Low-k Interconnects”
By: Philip G. Clark and Kurt Christenson
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“Non-Damaging Cleaning Processes for Porous Low-k Materials”
By: Philip G. Clark and Darren L. Moore
Photoresist removal using traditional plasma ash chemistries leads to severe degradation of low-k dielectric properties including increases in k-value and changes in critical dimensions. We present a new process using ozone-saturated, deionized water (DIO3) in a batch spray processor.
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“Rapid and Controlled Stripping of Thick Resists for Semiconductor BEOL Applications”
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"Characterizing Etch Residue Removal for Batch Processing of Spin-On Low-k Dielectric Materials"
Spin-on low-k dielectric materials, including SiLK and MSQ, are being integrated into BEOL Cu interconnect structures. Post-etch residue removal must selectively dissolve the organometallics without attacking the low-k or Cu film. We demonstrate such a substrate-safe stripper, GenSolve 670, in a batch spray system. A complete cycle time of 30 minutes is possible, providing a throughput near 200 wph.
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"Improved Post-etch Via Clean with Fluoride-based Semi-aqueous Chemistry using an Intermediate Rinse"
By: Jeffrey W. Butterbaugh
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- ORION®Single Wafer Cleaning System
- ZETA® Batch Spray System
- MAGELLAN® Batch Immersion System
