FEOL Critical Clean and Etch prepares the semiconductor wafer prior to film deposition-growth and before high-temperature operations, such as anneal and diffusion. These pre-clean steps must create ultra-clean surfaces with the ideal surface termination to produce high quality, defect-free films and contamination-free active areas.
Benefits
- FSI''s products and processes are engineered to provide very uniform etching while removing unwanted surface contamination.
- FSI''s advanced rinsing and drying techniques produce device surfaces free of water marks, metallic contamination and particles.
News
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FSI International Releases ORION® Single Wafer Cleaning System
- ORION®Single Wafer Cleaning System
- ZETA® Batch Spray System
- MERCURY® Semi-Auto Batch Spray System
- MAGELLAN® Batch Immersion System
Innovative closed-chamber design enables critical path cleaning capabilities for ultra shallow junctions, high-k/metal gates and metal capping layers at 32nm and below.
MINNEAPOLIS (November 3, 2008) — FSI International, Inc. (Nasdaq: FSII) a leading supplier of wafer processing, cleaning and surface conditioning equipment for semiconductor manufacturing, announced today the release of its new ORION® Single Wafer Cleaning System.
MoreYield improvement using the MAGELLAN® System’s flexibility to achieve recipe optimization
OTS (September 2008) -- In their FSI Knowledge Services™ Seminar presentation, Nirit Sofer and Lev Sherbelis of Numonyx confirmed significant yield gains in flash memory production after optimizing the SC1 cleaning process to increase particle removal efficiency (PRE), noting that the detailed optimization was enabled by the MAGELLAN® System’s flexible but precise recipe control of multiple process parameters (see Figure 1).
MoreFSI Receives U.S. Patent Strengthening Its Intellectual Property Portfolio for Surface Tension Gradient (STG®) Technology
OTS (February 2008) -- The U.S. Patent and Trademark Office has awarded FSI a patent for a method which improves rinsing and drying microelectronic devices in immersion tanks for front-end-of-line (FEOL) critical cleans. This patent further strengthens and broadens FSI’s patent portfolio in the area of surface tension gradient (STG®) rinse/dry process and provides IC makers with industry-leading rinse dry performance for 300mm FEOL critical cleaning at 65nm, 45nm, and future generations. The STG® process is currently used in the FSI MAGELLAN® immersion cleaning system.
MoreFirst High Throughput MAGELLAN® System Shipped for Production
OTS (July 2007) -- The first MAGELLAN® immersion cleaning system on the new high throughput platform has been shipped for use in several production applications at a major logic and memory manufacturer in the US. The MAGELLAN® system has seen widespread acceptance, with the number of installed systems doubling in the last two years. Currently tools are installed in all three major manufacturing regions, Asia, Europe and North America, in both logic and memory fabrication, and in 65nm production and 45nm development applications.
MoreFSI International Expands Its Technology Portfolio for Advanced High-k Gate Applications with Allowance of a New Patent
MINNEAPOLIS (June 26, 2007) -- FSI International, Inc. (Nasdaq: FSII) announced today that it received Notice of Allowance from the U.S. Patent and Trademark Office for a surface preparation method of forming an ultra-thin silicon oxide layer required prior to deposition of a high dielectric constant (high-k) film. This patent broadens FSI’s technology portfolio to further address the needs of IC manufacturers when implementing high-k technology in the fabrication of 45nm and 32nm devices.
MoreFSI International Receives U.S. Patent for Method of Combining Uniform Etching with Rinsing and Drying in a Single Immersion Tank
MINNEAPOLIS (May 16, 2007) -- FSI International, Inc. (Nasdaq: FSII) announced today that the U.S. Patent and Trademark Office has awarded the company a patent for a method which produces ultra-uniform etch results in combination with a rinse/dry step in a single immersion tank for front-end-of-line (FEOL) critical cleans. This advancement is part of FSI’s SymFlow™ technology and is integrated with FSI’s exclusive surface tension gradient (STG®) rinse/dry process for use in the MAGELLAN® Immersion Cleaning System.
MoreFSI International Receives Multi-Unit Order for its MAGELLAN® Immersion Cleaning System from Leading U.S. IC Manufacturer
MINNEAPOLIS (June 6, 2006) — FSI International, Inc. (Nasdaq: FSII) today announced that a world-leading U.S. IC manufacturer has placed a multi-unit order for its 200/300mm MAGELLAN® Immersion Cleaning System. This order is a result of the MAGELLAN system’s best-of-breed particle and etch uniformity performance. The tools will be used in manufacturing and are expected to ship during the first half of FSI’s fiscal 2007.
MoreThe MAGELLAN® System Delivers Proven Process Performance for 65nm Technology
OTS (February 2006) -- The MAGELLAN® Immersion Cleaning System has been qualified for 65nm baseline manufacturing. Top chipmakers using the system have confirmed notable process performance. The tool's 65nm process performance is highlighted by one customer's results for an oxide removal and surface preparation process.
MoreFSI International Introduces New Cleaning Processes for Advanced Technology Nodes New Processes Meet Customer Needs Well Ahead of ITRS Schedule
MINNEAPOLIS (June 30, 2005) -- FSI International, Inc. (Nasdaq: FSII) today announced new cleaning processes to meet the needs of leading IC makers well ahead of the International Technology Roadmap for Semiconductors (ITRS) guidelines for material loss. The ITRS calls for a maximum material loss per cleaning cycle of 0.4 angstrom at the 45nm technology node, while semiconductor manufacturers indicate their requirements are closer to 0.1 angstrom.
MoreFSI Receives Follow-on Order from Asian Foundry for ZETA® Spray Cleaning System
MINNEAPOLIS (Mar. 8, 2005) -- FSI International, Inc. (Nasdaq: FSII) today announced that it continues to see strong acceptance of its spray cleaning technology in Asia, as evidenced by a repeat order for its ZETA® Spray Cleaning System from an Asian foundry customer.
MoreFSI International Awarded U.S. Patent on Method for Etching High-k Films for Advanced Technology Nodes
MINNEAPOLIS (Feb. 15, 2005) -- FSI International, Inc. (Nasdaq: FSII), a manufacturer of capital equipment for the microelectronics industry, today announced that the U.S. Patent and Trademark Office has awarded the company a patent for a new process to etch high dielectric constant (high-k) films with high selectivity. The new process, which will be used at the 45-nm node and below, enables wet etching of high-k films – something not possible with traditional dielectric wet etch techniques.
MoreFSI International Receives Follow On Orders From International Customers For Its ZETA® Spray Cleaning System
MINNEAPOLIS (Dec. 21, 2004) -- FSI International, Inc. (Nasdaq: FSII) today announced that the company has received repeat orders for its 300-mm ZETA® Spray Cleaning System. The repeat order from a leading IC manufacturer based in Taiwan will be used for front-end-of-line (FEOL) surface preparation at the 90-nm technology node and the ZETA System ordered by a major microprocessor manufacturer will be used for back end applications.
MoreFSI International Surface Preparation Products Gain Momentum in Asia
MINNEAPOLIS (September 14, 2004) -- FSI International, Inc. (Nasdaq: FSII) today announced that its surface preparation technology platforms are experiencing broad adoption in Asia, with sales to customers in the region accounting for nearly 40 percent of all orders in the first nine months of fiscal year 2004, up from 11 percent in the first nine months of fiscal 2003.
MoreFSI International Receives Multiple ZETA® System Orders From Leading Global Integrated Circuit Manufacturers
MINNEAPOLIS (March 10, 2004) -- FSI International, Inc. (Nasdaq: FSII) today announced that during the second fiscal quarter the company received orders for multiple 200- and 300-mm ZETA® Spray Cleaning Systems from leading semiconductor manufacturers.
MorePublications
“Preparation, Characterization, and Damage-free Processing of Advanced Multiple-Gate FETs”
By: Jeffrey M. Lauerhaas, FSI International, Rinn Cleavelin and Weize Xiong, Texas Instruments, Koki Mochizuki, Kara Sherman, Hucheng Lee and Brian Clappin, KLA-Tencor and Thomas Schulz, Klaus Schruefer, Infineon Technologies
Advanced transistor structures, such as the Multiple-Gate FET (MuGFET), offer improved shortchannel effects control compared to the bulk-Si MOSFET [1]. Hence they may be adopted in CMOS technology as early as the 32nm technology generation [2]. MuGFET current conduction is on the sidewalls of silicon fins.
Request Article“New Technologies in Immersion Cleaning”
By: Weiping Ma, FSI International
Although immersion cleaning has been a mature technology for wafer cleaning for many years, there are still advancements made today, especially targeted for 90nm and below technology nodes. In this column, we will introduce some of FSI International’s innovations in immersion cleaning.
Request Article“45nm Node Wafer Cleaning Techniques For Meeting the Challenges of Advanced Semiconductor Manufacturing”
By: Jeffery Butterbaugh, FSI International and Charles Gould, Entegris
On December 13, 2005, the most recent version of International Technology Roadmap for Semiconductors (ITRS) was introduced during a public conference in Seoul, Korea. From the presentations regarding semiconductor design and manufacturing, it is certain that the future of semiconductor manufacturing will continue to present significant challenges for both front-end-of-line (FEOL) and back-end-of-line (BEOL) surface preparation and critical cleaning steps.
Request Article"Reducing Time in Batch Cleaning"
By: Jeffrey Butterbaugh, FSI International
Wafer cleaning represents up to 15% of the total process steps to build an advanced, 90-nm semiconductor device and is still mainly carried out in batch processes. Performance and throughput advantages are the main reasons for the persistence of batch processing in cleaning. However, concerns about cycle time are driving development of single wafer cleaning processes. Jeffery W. Butterbaugh of FSI International looks at alternatives for maintaining performance and throughput while realizing gains in productivity for cleaning processes.
“Single-Tank Processing Demonstrates Immersion Batch Cleaning for 65nm IC's (Advanced Immersion Batch Cleaning Processes Using Advanced and Flexible Configurations)”
By: Jeffery W. Butterbaugh and Nam-Pyo Lee
Request Article"Strategies for Second-Hand Equipment in China"
While used equipment has been widely used in China and contributing to a strong advantage in low-cost manufacturing, the Chinese IC industry also needs technology upgrade to continue the rapid growth. Can 2nd hand equipment continue to be useful at the next nodes? We offer strategies and examples from our work with leading IC makers worldwide.
"Rinsing: A Critical Process in Particle Removal"
By: Kurt Christenson
Rinsing is a critical process in particle removal. This paper examines fundamental mechanisms of rinsing and applies these principals to the development of ramped rinsing in spray cleaning. Results include better particle removal and reduced water consumption.
“Uniform Ultra-thin Oxide Growth for High-k Pre-clean”
By: Jeffery Butterbaugh
To continue the scaling of integrated circuits, the standard silicon oxide gate is being replaced with higher dielectric constant (high-k) materials, which must be deposited onto a substrate terminated with an ultra-thin oxide layer. We describe a novel combination of saturated oxide growth and uniform oxide etch as the final step of a pre-clean process for high-k gate dielectrics.
Request Article“Better Repeatability Through Automated Etch Control”
By: Jerry Zhao (ASMC) and Mark Ge (FSI)
For customers using spray processors for pre-diffusion clean, the FSI Etch Control option automatically controls the length of etch steps by measuring and adjusting for concentration of the etchant and wafer temperature. For the oxide loss target of 105Å, ASMC achieved reduction of the standard deviation from 6.76Å to 2.10Å, and of the repeatability deviation from 6.45% to 1.99%.
Request Article"HF Based Cleaning Processes for Current Applications and New Materials in an Advanced Immersion Cleaning System"
By: Nampyo Lee
Dilute HF (DHF) “cleans” is the most widely used cleaning method in semiconductor processing. In 300mm manufacturing, DHF processes must be exceptionally controlled to avoid particle deposition from adjacent, closely spaced (5mm) wafers and to result in good thin oxide etch uniformity.
Request Article"Minimizing Oxide Loss in Immersion SC1 Process"
By Jeff Butterbaugh, Steve Loper and Tom Wagener
As IC scaling continues to push the limits, device manufacturers need to be able to clean without etch and thereby maintain device structure integrity. We have studied particle removal efficiency as a function of several SC1/megasonics parameters at low oxide loss conditions.
Request Article"Better Wet Bench Productivity through a New Method of Rinse Optimization"
Conventional wet chemistry processing in semiconductor manufacturing is virtually under attack to reduce chemical volumes, water consumption, system footprint, and overall cost; the needs are even more severe when you consider 300mm wafer processing. In developing new capability to meet these demands, a group of engineers have come up with a novel method of monitoring rinse efficiency. The method itself attacks conventional wisdom about rinse efficiency.
"Better HF ETch Uniformity with Single-Tank Approach"
Immersion processing, a tried-and-true method for wafer cleaning, has been redesigned from the ground up for 100nm and future technology nodes, as stricter processing tolerances are required. A new batch, single-tank process can achieve excellent uniformity in critical dilute HF (DHF) etches, and provide the uniformity of a dual-tank process in a single-tank footprint. The symmetrical, continuous-flow process eliminates the need for a dedicated HF bath, leading to an even smaller footprint. In cases where SC1 or ozonated DI water steps precede the DHF step, an additional dedicated rinse bath can also be eliminated.
“An Integrated Wet Chemical Etch-Strip-Clean Sequence,” Solid State Technology
An investigation was conducted to determine the source of a yield-limiting defect identified on all product types at a wafer fab. The defect was isolated to patterning operations in the frontend section of the device process where a conventional multistep sequence was used. The problem was traced to a wet chemical buffered oxide etching step and attributed to drying wafers before ashing the resist film.
Request Article