FEOL Strip and Clean processes include removing photoresist films or ashing residues after ion implantation and dry etch operations. These processes must completely remove patterned photoresist films or ash residues while minimizing the loss of device materials.
Benefits
- FSI's revolutionary ViPR™ resist strip process is equally effective at removing either photoresist or its ash residues.
- FSI's ViPR™ resist strip process can eliminate ashing for 80% of the implantation masks, resulting in significant reductions in material loss, cycle time and capital investment.
News
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FSI International Releases ORION® Single Wafer Cleaning System
- ORION®Single Wafer Cleaning System
- ZETA® Batch Spray System
- MERCURY® Semi-Auto Batch Spray System
- MAGELLAN® Batch Immersion System
Innovative closed-chamber design enables critical path cleaning capabilities for ultra shallow junctions, high-k/metal gates and metal capping layers at 32nm and below.
MINNEAPOLIS (November 3, 2008) — FSI International, Inc. (Nasdaq: FSII) a leading supplier of wafer processing, cleaning and surface conditioning equipment for semiconductor manufacturing, announced today the release of its new ORION® Single Wafer Cleaning System.
MoreControlling Dissolved Oxygen in Cleaning Processes
OTS (September 2008) -- Dissolved gases have long been known to have significant impact on wet cleaning processes. Dissolved oxygen in rinse water contributes to surface oxidation and watermark formation during wafer drying [1-2]. Dissolved gases can affect megasonics processes and are often controlled in order to optimize particle removal efficiency and prevent pattern damage [3]. In addition, dissolved CO2 is well-known to form carbonic acid, affecting the pH of liquid cleaning solutions. More recently, there is an increased concern about the effect of dissolved oxygen when cleaning surfaces with different metals exposed.
MoreFSI co-authors paper at the 17th International Conference on Ion Implantation Technology
OTS (September 2008) -- FSI co-authors paper at the 17th International Conference on Ion Implantation Technology (IIT 2008) in Monterey, California, June 8-13, 2008
The International Conference on Ion Implantation Technology is held every two years at different locations around the world. This Conference Series is the premier world meeting for the presentation of the latest advances in all aspects of ion implantation. The Conference consists of invited presentations as well as selected contributed presentations and posters.
MoreApprecia Technology, Inc. presents at the Electronic Journal 186th Technical Symposium
OTS (September 2008) -- Apprecia Technology, Inc. presents at the Electronic Journal 186th Technical Symposium - Exhaustive Study for 2008 ULSI Surface Cleaning and Drying Technology - in Tokyo, August 28, 2008
Electronic Journal in Japan sponsors many technical symposia. Each year one of the symposia is focused on cleaning technology in IC manufacturing. In 2008, the focus of this symposium was on cleaning challenges for 45nm and 32nm technology generations.
MoreResist Removal Walks a Tightrope
At the 32 nm technology node and beyond, the most critical front-end-of-line (FEOL) cleans are during ultrashallow junction (USJ) formation, with an International Technology Roadmap for Semiconductors' (ITRS) target of 0.3 Å/clean of silicon loss. Meeting this challenge is most difficult for resist removal following high-dose implants.
Increasing Demands Require New Look at Wafer Cleans
As device structures scale down, it is getting increasingly difficult to achieve low material loss while still removing particles. It is also getting more difficult to keep from damaging, attacking or otherwise modifying surrounding materials and structures — including doped silicon loss, changes in the k values of low-k dielectrics, metal gate corrosion, pattern collapse, and more.
MoreFSI Sponsors and Presents at the 2008 9th International Symposium on Ultra Clean Processing of Semiconductor Surfaces
OTS (September 2008) -- The Symposium on Ultra Clean Processing of Semiconductor Surfaces (UCPSS) objective is to increase the level of understanding on ultra-clean processing technology in all steps of IC-production.
The conference, which was held September 21-24 in Bruges, Belgium, included invited presentations as well as selected contributing presentations and posters.
MoreFSI was a Proud Sponsor of the 5th Semiconductor International China Wafer Cleaning Seminar Held 15 October 2008 in Shanghai
OTS (September 2008) -- The The SI China conference theme was Applications and Challenges in Cleaning Technology at the Age of Deep Submicron and emphasized practical and next-generation technologies, including:
More
FSI Receives U.S. Patent Strengthening Its Intellectual Property Portfolio for Surface Tension Gradient (STG®) Technology
OTS (February 2008) -- The U.S. Patent and Trademark Office has awarded FSI a patent for a method which improves rinsing and drying microelectronic devices in immersion tanks for front-end-of-line (FEOL) critical cleans. This patent further strengthens and broadens FSI’s patent portfolio in the area of surface tension gradient (STG®) rinse/dry process and provides IC makers with industry-leading rinse dry performance for 300mm FEOL critical cleaning at 65nm, 45nm, and future generations. The STG® process is currently used in the FSI MAGELLAN® immersion cleaning system.
MoreFSI International’s ZETA® System ViPR™ Process Identified as a Key Technology for Ultra-High Dose Ion Implantation in CMOS Applications
MINNEAPOLIS (June 17, 2008) -- FSI International, Inc. (Nasdaq: FSII) announced today that a paper jointly presented by Hynix Semiconductor, Inc.; Varian Semiconductor Equipment Associates, Inc.; Nanometrics Incorporated and FSI identifies the ZETA® Spray Cleaning System with ViPR™ technology as a key step in the integration of ultra-high dose PLAD (plasma doping) ion implantation. The paper was presented at the 17th International Conference on Ion Implantation Technology held June 8-13, 2008, in Monterey, California. The ViPR process is uniquely-capable of removing photoresist hardened by exposure to high-dose ion bombardment without the surface damage and material loss caused by traditional techniques.
MoreFSI International Receives Multiple ZETA® Spray Cleaning System Orders with ViPR™ Technology for Wet Resist Stripping and Metal Film Etching after Salicide Formation
MINNEAPOLIS (April 15, 2008) -- FSI International, Inc. (Nasdaq: FSII), a leading manufacturer of wafer cleaning systems used in the fabrication of integrated circuits, announced today that it has received orders for its ZETA® spray cleaning systems with ViPR™ technology from customers in Korea, Japan and Europe. These purchases are from new users of FSI’s ViPR process and demonstrate the growing adoption of this innovative solution, driven by its ability to address critical advanced IC manufacturing cost and integration concerns during photoresist stripping and salicide formation. The systems are scheduled to ship in the third quarter of fiscal 2008.
MoreZETA® Spray Cleaning System’s ViPR™ Process for Ashless Photoresist Stripping Reduces Material Loss and Chemical Costs While Improving Throughput
OTS (February 2008) -- In the latest generation ZETA® system, the new ViPR™ process now offers two recipe types ViPR™ and ViPR™+. The new ViPR™ technology further improves the established ViPR™ process by optimizing conditions to achieve the highest stripping levels with the lowest possible material loss. This is critical for both Logic and DRAM manufacturers.
MoreFSI Presents on the Financial Benefits of All-Wet Photoresist Removal for 200mm in Wuxi, China
OTS (February 2008) -- At the November 2007 China IC Industry Development Conference in Wuxi, China, James Chu, FSI field application engineering manager for SE Asia and Great China presented the “The Financial Benefits of All Wet Photoresist Removal for 200mm.”
MoreFSI Presents Papers on Yield Improvement Using Cryogenic Aerosol for BEOL Defect Removal and Wet Resist Strip Capability vs. Implant Energy at ECS
OTS (February 2008) -- FSI presented at the 10th International Symposium on Cleaning and Surface Conditioning Technology in Semiconductor Device Manufacturing at the October 2007, Electrochemical Society Meeting in Washington, D.C.
MoreFSI Presents the Advantages of Batch Spray Processing for Superior All-Wet Photoresist Stripping and Film Removal in China and Korea
OTS (February 2008) -- “Batch Spray processing for Superior Photoresist Stripping and Film Removal process” was presented at the August 2007 SI China Wafer Cleaning Seminar in Shanghai, China, by James Chu, FSI field application engineering manager for SE Asia and Great China; and at the September 2007, 6th Korean Surface Cleaning Users Group meeting in Seoul, Korea, by Andy Lee, FSI spray applications section manager.
MoreFirst High Throughput MAGELLAN® System Shipped for Production
OTS (July 2007) -- The first MAGELLAN® immersion cleaning system on the new high throughput platform has been shipped for use in several production applications at a major logic and memory manufacturer in the US. The MAGELLAN® system has seen widespread acceptance, with the number of installed systems doubling in the last two years. Currently tools are installed in all three major manufacturing regions, Asia, Europe and North America, in both logic and memory fabrication, and in 65nm production and 45nm development applications.
MoreAll-wet stripping of high dose implanted photoresist qualified and in production
OTS (July 2007) -- All-wet stripping of high dose implanted photoresist qualified and in production
Jeffery W. Butterbaugh, FSI International Chief Technologist
All-wet resist stripping has been a major focus of cleaning equipment suppliers for the past two years. The desire by IC manufacturers for all-wet photoresist stripping is driven by a need to decrease material loss and eliminate the side effects of plasma ashing during the photoresist stripping process.
MoreSamsung Presents Results of ViPR™ Process Joint Development Project
OTS (July 2007) -- At the April FSI Knowledge Services™ Seminar held in Seoul, Korea, Mr. Kwang Wook Lee of Samsung Electronics presented the results of a year-long joint development project to evaluate and improve the performance of FSI’s ViPR™ all wet stripping process on photoresist used in high dose implant processes. The JDP focused on plasma doping applications and successfully qualified the ViPR™ process for increased stripping capability, reduced material loss, and better electrical characteristics.
MoreFSI International Expands Its Technology Portfolio for Advanced High-k Gate Applications with Allowance of a New Patent
MINNEAPOLIS (June 26, 2007) -- FSI International, Inc. (Nasdaq: FSII) announced today that it received Notice of Allowance from the U.S. Patent and Trademark Office for a surface preparation method of forming an ultra-thin silicon oxide layer required prior to deposition of a high dielectric constant (high-k) film. This patent broadens FSI’s technology portfolio to further address the needs of IC manufacturers when implementing high-k technology in the fabrication of 45nm and 32nm devices.
MoreITRS Timing Adjustments Affect New Surface Preparation Requirements
OTS (February 2007)
MoreNew Hot Acid Cleaning Process Eliminates Etching and Damage Associated with SC1 and Megasonics
OTS (February 2007) -- FSI has developed a proprietary process for removing particles added by hot acid processes and avoids the unwanted etching and damage that can occur with conventional cleaning processes.
MorePre-treatment Suppresses Native Oxide Loss and Silicon Attack During Hot Phosphoric Acid Nitride Etch Process
OTS (November 2006) -- Using its MAGELLAN® Immersion Cleaning System, FSI has demonstrated the ability of proprietary pretreatment steps to suppress native oxide loss and silicon attack during nitride etch with hot phosphoric acid. Normally, hot phosphoric acid will quickly etch away the native oxide exposing the underlying silicon to attack.
MoreEnhanced MAGELLAN® Platform Offers World Class or HVM Throughput Up To 400 WPH
OTS (November 2006) -- FSI’s newly enhanced MAGELLAN® Immersion Cleaning System now offers throughput up to 400 WPH. Throughput enhancing improvements include a faster wafer handling robot and an optional dual robot configuration.
MoreFSI’s ViPR™ Process Production Qualified by Major Semiconductor Manufacturer
OTS (November 2006) -- FSI’s new ViPR™ process running on the ZETA® G3 platform is being used in several fabs of a major Asian semiconductor manufacturer. This represents rapid and significant progress in the acceptance of the ViPR™ process since our last report three months ago when it was still in the initial stages of a multi-tiered qualification process.
MoreFSI International Introduces New Silicon Nitride Selective Etch Processes using its MAGELLAN® Immersion Cleaning System
MINNEAPOLIS (November 14, 2006) -- FSI International, Inc. (Nasdaq: FSII) announced today new selective nitride etch processes that suppress oxide and silicon attack without generating high particle counts using its MAGELLAN® Immersion Cleaning System. These applications were developed and proven in the FSI laboratory on customer wafers as part of a 45nm advanced technology program. These applications will be useful for older technology generations as well.
MoreMAGELLAN® Immersion Cleaning System Nitride Etch Demonstrates Unrivaled Selectivity and Uniformity
OTS (July 2006)-- Nitride etch using the MAGELLAN® immersion cleaning system has demonstrated unrivaled selectivity and uniformity. In selectivity tests, the system has repeatedly removed up to 3,500Å of nitride with no measurable oxide loss. Uniformity within wafers averages 1.7 percent at one sigma for 300 mm wafers.
MoreZETA® G3 Spray Cleaning System Accepted and in Production Qualification
OTS (July 2006) -- The first ZETA® G3 spray cleaning systems, shipped March 2006, have been accepted and are in the process of production qualification. The ZETA G3 is the third generation on the ZETA platform.
MoreFSI International Receives Multi-Unit Order for its MAGELLAN® Immersion Cleaning System from Leading U.S. IC Manufacturer
MINNEAPOLIS (June 6, 2006) — FSI International, Inc. (Nasdaq: FSII) today announced that a world-leading U.S. IC manufacturer has placed a multi-unit order for its 200/300mm MAGELLAN® Immersion Cleaning System. This order is a result of the MAGELLAN system’s best-of-breed particle and etch uniformity performance. The tools will be used in manufacturing and are expected to ship during the first half of FSI’s fiscal 2007.
MoreFSI Introduces New ViPR™ Technology for Ash-Free, Wet Resist Stripping Technology Available on ZETA® G3 Spray Cleaning Platform
MINNEAPOLIS (March 20, 2006) -- FSI International, Inc. (Nasdaq: FSII) today introduced its new ViPR™ technology. This innovative technology eliminates the need for ashing on most implanted photoresist stripping steps, including 1x1017 ions/cm2 plasma doped (PLAD) photoresist. The ViPR technology is available on FSI’s ZETA® G3 Spray Cleaning Platform.
MoreCleaning with Low Material Loss Requires an Integrated Approach
OTS (February 2006) -- Jeffery W. Butterbaugh, FSI International Chief Technologist
Over the past few years, a large portion of the research and development in cleaning processes has focused on achieving high-efficiency particle removal while minimizing damage and material loss.
MoreThe MAGELLAN® System Delivers Proven Process Performance for 65nm Technology
OTS (February 2006) -- The MAGELLAN® Immersion Cleaning System has been qualified for 65nm baseline manufacturing. Top chipmakers using the system have confirmed notable process performance. The tool's 65nm process performance is highlighted by one customer's results for an oxide removal and surface preparation process.
MoreFSI International Launches the EcoBlend™ Process Series of Cost-Effective Dilute Acid Cleaning Solutions for Post-Ash Residue Removal
MINNEAPOLIS (August 2, 2005) -- FSI International, Inc. (Nasdaq: FSII) today announced a new family of dilute acid cleans, called the EcoBlend™ Processes, for cost-effective and environmentally friendly removal of post-ash residues. Used for aluminum and tungsten interconnect cleaning applications, this family of chemical processes gives IC manufacturers alternatives to high-cost specialty chemicals.
MoreFSI International Introduces New Cleaning Processes for Advanced Technology Nodes New Processes Meet Customer Needs Well Ahead of ITRS Schedule
MINNEAPOLIS (June 30, 2005) -- FSI International, Inc. (Nasdaq: FSII) today announced new cleaning processes to meet the needs of leading IC makers well ahead of the International Technology Roadmap for Semiconductors (ITRS) guidelines for material loss. The ITRS calls for a maximum material loss per cleaning cycle of 0.4 angstrom at the 45nm technology node, while semiconductor manufacturers indicate their requirements are closer to 0.1 angstrom.
MoreFSI Receives Follow-on Order from Asian Foundry for ZETA® Spray Cleaning System
MINNEAPOLIS (Mar. 8, 2005) -- FSI International, Inc. (Nasdaq: FSII) today announced that it continues to see strong acceptance of its spray cleaning technology in Asia, as evidenced by a repeat order for its ZETA® Spray Cleaning System from an Asian foundry customer.
MoreFSI International Awarded U.S. Patent on Method for Etching High-k Films for Advanced Technology Nodes
MINNEAPOLIS (Feb. 15, 2005) -- FSI International, Inc. (Nasdaq: FSII), a manufacturer of capital equipment for the microelectronics industry, today announced that the U.S. Patent and Trademark Office has awarded the company a patent for a new process to etch high dielectric constant (high-k) films with high selectivity. The new process, which will be used at the 45-nm node and below, enables wet etching of high-k films – something not possible with traditional dielectric wet etch techniques.
MoreFSI International Receives Follow On Orders From International Customers For Its ZETA® Spray Cleaning System
MINNEAPOLIS (Dec. 21, 2004) -- FSI International, Inc. (Nasdaq: FSII) today announced that the company has received repeat orders for its 300-mm ZETA® Spray Cleaning System. The repeat order from a leading IC manufacturer based in Taiwan will be used for front-end-of-line (FEOL) surface preparation at the 90-nm technology node and the ZETA System ordered by a major microprocessor manufacturer will be used for back end applications.
MoreFSI International Surface Preparation Products Gain Momentum in Asia
MINNEAPOLIS (September 14, 2004) -- FSI International, Inc. (Nasdaq: FSII) today announced that its surface preparation technology platforms are experiencing broad adoption in Asia, with sales to customers in the region accounting for nearly 40 percent of all orders in the first nine months of fiscal year 2004, up from 11 percent in the first nine months of fiscal 2003.
MoreFSI International Receives Multiple ZETA® System Orders From Leading Global Integrated Circuit Manufacturers
MINNEAPOLIS (March 10, 2004) -- FSI International, Inc. (Nasdaq: FSII) today announced that during the second fiscal quarter the company received orders for multiple 200- and 300-mm ZETA® Spray Cleaning Systems from leading semiconductor manufacturers.
MorePublications
“Wet Resist Strip Capability vs. Implant Energy”
By: Kurt K. Christenson, FSI International
Implant doses greater than 5E14 atoms/cm2 can create an amorphous carbon like damage layer (crust) that is difficult to dissolve with wet chemistries.
Request Article“All Wet Stripping of Implanted Photoresist”
By: Kurt K. Christenson, Jeffery W. Butterbaugh, Thomas J. Wagener, Nam Pyo Lee, Brent Schwab, Michael Fussy, John Diedrick, FSI International
A new all-wet piranha-based process capable of reaching 200°C on-wafer temperatures has been demonstrated for stripping implanted photoresist.
Request Article“A High-Temperature Batch-Spray Process for Implanted Resist Stripping”
By: Jeffery Butterbaugh, Kurt Christenson and Nam Pyo Lee
Photoresist stripping in IC manufacturing has become more challenging as the number of photoresist levels has increased, while at the same time allowable material loss and surface damage has decreased. Heavily implanted photoresist is especially challenging due to the dehydrogentated, amorphous carbon layer that forms on the surface.
Request Article“45nm Node Wafer Cleaning Techniques For Meeting the Challenges of Advanced Semiconductor Manufacturing”
By: Jeffery Butterbaugh, FSI International and Charles Gould, Entegris
On December 13, 2005, the most recent version of International Technology Roadmap for Semiconductors (ITRS) was introduced during a public conference in Seoul, Korea. From the presentations regarding semiconductor design and manufacturing, it is certain that the future of semiconductor manufacturing will continue to present significant challenges for both front-end-of-line (FEOL) and back-end-of-line (BEOL) surface preparation and critical cleaning steps.
Request Article“The Litmus Test ’Selective Etching of High-k Dielectric Films’”
By: Kurt Christenson
Request Article"Strategies for Second-Hand Equipment in China"
While used equipment has been widely used in China and contributing to a strong advantage in low-cost manufacturing, the Chinese IC industry also needs technology upgrade to continue the rapid growth. Can 2nd hand equipment continue to be useful at the next nodes? We offer strategies and examples from our work with leading IC makers worldwide.
"Batch Spray Processors: Reducing Cycle Time, Improving Performance"
By: Erik Olson
Through rinse optimization, we have developed the FlashClean™ Advantage package for the ZETA® Spray Cleaning System. As shown in our work and at Texas Instruments production facility, the FlashClean™ Advantage not only produces manufacturing advantages of reduced cycle time and chemical and water consumption but also improves particle performance for the 65nm technology node. The benefits are widely applicable to all spray applications.
“Selective Etching of High-k”
Solid State Technology Web Exclusive
The deposition of blanket films with a subsequent etch after gate patterning remains the leading candidate for integrating high-k gate dielectrics at the 70nm node.
Request Article“An Integrated Wet Chemical Etch-Strip-Clean Sequence,” Solid State Technology
An investigation was conducted to determine the source of a yield-limiting defect identified on all product types at a wafer fab. The defect was isolated to patterning operations in the frontend section of the device process where a conventional multistep sequence was used. The problem was traced to a wet chemical buffered oxide etching step and attributed to drying wafers before ashing the resist film.
Request Article