“45nm Node Wafer Cleaning Techniques For Meeting the Challenges of Advanced Semiconductor Manufacturing,” by Jeffery Butterbaugh, FSI International and Charles Gould, Entegris, published in Semiconductor Manufacturing, May 2006

Abstract: On December 13, 2005, the most recent version of International Technology Roadmap for Semiconductors (ITRS) was introduced during a public conference in Seoul, Korea. From the presentations regarding semiconductor design and manufacturing, it is certain that the future of semiconductor manufacturing will continue to present significant challenges for both front-end-of-line (FEOL) and back-end-of-line (BEOL) surface preparation and critical cleaning steps. This article reviews some of the most pressing challenges facing end-users, process tool manufacturers and materials suppliers, challenges that must be addressed in order to meet the progression of the ITRS.

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“An Integrated Wet Chemical Etch-Strip-Clean Sequence,” Solid State Technology, October 2000

Abstract: An investigation was conducted to determine the source of a yield-limiting defect identified on all product types at a wafer fab. The defect was isolated to patterning operations in the frontend section of the device process where a conventional multistep sequence was used. The problem was traced to a wet chemical buffered oxide etching step and attributed to drying wafers before ashing the resist film. A novel solution was implemented using an integrated centrifugal spray process, which resulted in defect elimination, increased device yields, and fewer process steps.

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“Better HF Etch Uniformity with Single-Tank Approach,” Semiconductor International, volume 25, number 9, page 46, August 2002

Abstract: Immersion processing, a tried-and-true method for wafer cleaning, has been redesigned from the ground up for 100nm and future technology nodes, as stricter processing tolerances are required. A new batch, single-tank process can achieve excellent uniformity in critical dilute HF (DHF) etches, and provide the uniformity of a dual-tank process in a single-tank footprint. The symmetrical, continuous-flow process eliminates the need for a dedicated HF bath, leading to an even smaller footprint. In cases where SC1 or ozonated DI water steps precede the DHF step, an additional dedicated rinse bath can also be eliminated.

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“Better Repeatability Through Automated Etch Control,” by Jerry Zhao (ASMC) and Mark Ge (FSI), published in Semiconductor Technology, volume 29, issue 5, pages 31-34, May 2004

Abstract: For customers using spray processors for pre-diffusion clean, the FSI Etch Control option automatically controls the length of etch steps by measuring and adjusting for concentration of the etchant and wafer temperature. For the oxide loss target of 105Å, ASMC achieved reduction of the standard deviation from 6.76Å to 2.10Å, and of the repeatability deviation from 6.45% to 1.99%.

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“Better Wet Bench Productivity through a New Method of Rinse Optimization,” Solid State Technology, volume 47, number 4, page 41, April 2003

Abstract: Conventional wet chemistry processing in semiconductor manufacturing is virtually under attack to reduce chemical volumes, water consumption, system footprint, and overall cost; the needs are even more severe when you consider 300mm wafer processing. In developing new capability to meet these demands, a group of engineers have come up with a novel method of monitoring rinse efficiency. The method itself attacks conventional wisdom about rinse efficiency.

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"Front End Processes," by Jeffrey Butterbaugh, FSI Internatinal; Larry Larson, SEMATECH and Texas Instruments; Raj Jammy, SEMATECH

Scope: The Front End Processes (FEP) chapter of the ITRS (International Technology Roadmap for Semiconductors) focuses on future process requirements and potential solutions for the continued scaling of devices based on field effect transistors (FET); including high-performance, lowoperating power and low-standby power logic devices; dynamic random access memory (DRAM) devices; and nonvolatile memory devices. This chapter defines comprehensive future requirements and potential solutions for the key front end wafer fabrication process technologies and materials associated with these devices. It addresses equipment and materials, as well as unit and integrated processes beginning with the substrate and extending through contact silicidation and deposition of strain layers. This chapter also addresses fabrication of storage nodes for the various memory devices.

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"HF Based Cleaning Processes for Current Applications and New Materials in an Advanced Immersion Cleaning System," by Nampyo Lee, presented at SEMICON Korea 2004, February 18-20, 2004

Abstract: Dilute HF (DHF) “cleans” is the most widely used cleaning method in semiconductor processing. In 300mm manufacturing, DHF processes must be exceptionally controlled to avoid particle deposition from adjacent, closely spaced (5mm) wafers and to result in good thin oxide etch uniformity. At the same time, device technology advances have introduced new materials such as low-k and high-k and drive new DHF applications. We show the MAGELLAN^® 300 STG^® Immersion Cleaning System’s ability for precise, repeatable processes on a variety of surfaces, including low-k and high-k.

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"Minimizing Oxide Loss in Immersion SC1 Process," by Jeff Butterbaugh, Steve Loper and Tom Wagener, presented at ECS Meeting, October 13-16, 2003

Abstract: As IC scaling continues to push the limits, device manufacturers need to be able to clean without etch and thereby maintain device structure integrity. We have studied particle removal efficiency as a function of several SC1/megasonics parameters at low oxide loss conditions. Traditional immersion and spray methods lose particle removal effectiveness at oxide loss of 3Å. In order to achieve oxide loss of only 1Å, we have developed a modified megasonics method that has been shown to be effective on 60nm wide polysilicon lines with an aspect ratio of over 3.0.

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“New Technologies in Immersion Cleaning,” by Weiping Ma, FSI International

Abstract: Although immersion cleaning has been a mature technology for wafer cleaning for many years, there are still advancements made today, especially targeted for 90nm and below technology nodes. In this column, we will introduce some of FSI International’s innovations in immersion cleaning.

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“Preparation, Characterization, and Damage-free Processing of Advanced Multiple-Gate FETs,” Jeffrey M. Lauerhaas, FSI International, Rinn Cleavelin and Weize Xiong, Texas Instruments, Koki Mochizuki, Kara Sherman, Hucheng Lee and Brian Clappin, KLA-Tencor and Thomas Schulz, Klaus Schruefer, Infineon Technologies, to be published in the proceedings of the 2006 UCPSS.

Introduction: Advanced transistor structures, such as the Multiple-Gate FET (MuGFET), offer improved shortchannel effects control compared to the bulk-Si MOSFET [1]. Hence they may be adopted in CMOS technology as early as the 32nm technology generation [2]. MuGFET current conduction is on the sidewalls of silicon fins. Thus tall fins are desirable for high drive current per unit footprint. At the same time, short channel effect (SCE) control requires narrow fin width. Therefore, for the 32nm technology generation, silicon fin width is expected to be ~15nm while silicon fin height will be ~50nm. Such tall and narrow features present unique challenges to front end cleaning and defect inspection, which must be addressed before MuGFETs can be introduced into a manufacturing environment. In this paper we present a silicon fin stability study to address these challenges. Currently available inspection and cleaning technologies in this work have demonstrated the ability to inspect with a high defect of interest capture rate and to clean the silicon fins without damage. Pre- and post-inspection indicate no damage to the silicon fins for each of the three cleaning technologies.

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“Reducing Time in Batch Cleaning,” by Jeffery Butterbaugh, FSI International

Abstract: Wafer cleaning represents up to 15% of the total process steps to build an advanced, 90-nm semiconductor device and is still mainly carried out in batch processes. Performance and throughput advantages are the main reasons for the persistence of batch processing in cleaning. However, concerns about cycle time are driving development of single wafer cleaning processes. Jeffery W. Butterbaugh of FSI International looks at alternatives for maintaining performance and throughput while realizing gains in productivity for cleaning processes.

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“Rinsing: A Critical Process in Particle Removal,” by Kurt Christenson

Abstract: Rinsing is a critical process in particle removal. This paper examines fundamental mechanisms of rinsing and applies these principles to the development of ramped rinsing in spray cleaning. Results include better particle removal and reduced water consumption.

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“Single-Tank Processing Demonstrates Immersion Batch Cleaning for 65nm IC's (Advanced Immersion Batch Cleaning Processes Using Advanced and Flexible Configurations),” by Jeffery W. Butterbaugh and Nam-Pyo Lee, FSI International

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“Strategies for Second-Hand Equipment in China,”

Abstract: While used equipment has been widely used in China and contributing to a strong advantage in low-cost manufacturing, the Chinese IC industry also needs technology upgrade to continue the rapid growth. Can 2nd hand equipment continue to be useful at the next nodes? We offer strategies and examples from our work with leading IC makers worldwide.

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“Uniform Ultra-thin Oxide Growth for High-k Pre-clean,” by Jeffery Butterbaugh (FSI), Proceedings: Ultra Clean Processing of Silicon Surfaces, September, 2004

Abstract: To continue the scaling of integrated circuits, the standard silicon oxide gate is being replaced with higher dielectric constant (high-k) materials, which must be deposited onto a substrate terminated with an ultra-thin oxide layer. We describe a novel combination of saturated oxide growth and uniform oxide etch as the final step of a pre-clean process for high-k gate dielectrics.

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“45nm Node Wafer Cleaning Techniques For Meeting the Challenges of Advanced Semiconductor Manufacturing,” by Jeffery Butterbaugh, FSI International and Charles Gould, Entegris, published in Semiconductor Manufacturing, May 2006

Abstract: On December 13, 2005, the most recent version of International Technology Roadmap for Semiconductors (ITRS) was introduced during a public conference in Seoul, Korea. From the presentations regarding semiconductor design and manufacturing, it is certain that the future of semiconductor manufacturing will continue to present significant challenges for both front-end-of-line (FEOL) and back-end-of-line (BEOL) surface preparation and critical cleaning steps. This article reviews some of the most pressing challenges facing end-users, process tool manufacturers and materials suppliers, challenges that must be addressed in order to meet the progression of the ITRS.

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“A High-Temperature Batch-Spray Process for Implanted Resist Stripping,” by Jeffery Butterbaugh, Kurt Christenson and Nam Pyo Lee, FSI International, published in Solid State Technology, May 2006

Abstract: Photoresist stripping in IC manufacturing has become more challenging as the number of photoresist levels has increased, while at the same time allowable material loss and surface damage has decreased. Heavily implanted photoresist is especially challenging due to the dehydrogentated, amorphous carbon layer that forms on the surface. Improvements to the standard sulfuric acid/hydrogen peroxide (“piranha”) resist stripping process have been made in a batch spray system to achieve on-wafer temperatures above 200°C. This has enabled the wet stripping of implanted photoresist exposed to doses greater than 1x10¹⁵ ions/cm². This capability can eliminate the need for ashing on a large number of implanted photoresist stripping steps, reducing surface damage and material loss, and also improving overall IC manufacturing cycle time.

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“All Wet Stripping of Implanted Photoresist,” by Kurt K. Christenson, Jeffery W. Butterbaugh, Thomas J. Wagener, Nam Pyo Lee, Brent Schwab, Michael Fussy, John Diedrick, FSI International, to be published in the proceedings of the 2006 UCPSS

Summary: A new all-wet piranha-based process capable of reaching 200°C on-wafer temperatures has been demonstrated for stripping implanted photoresist. Results indicate that this process should be able to strip over 80% of the implanted photomask levels currently used to produce logic devices, but with material and dopant loss levels superior to traditional ash+wet processes.

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“An Integrated Wet Chemical Etch-Strip-Clean Sequence,” Solid State Technology, October 2000

Abstract: An investigation was conducted to determine the source of a yield-limiting defect identified on all product types at a wafer fab. The defect was isolated to patterning operations in the frontend section of the device process where a conventional multistep sequence was used. The problem was traced to a wet chemical buffered oxide etching step and attributed to drying wafers before ashing the resist film. A novel solution was implemented using an integrated centrifugal spray process, which resulted in defect elimination, increased device yields, and fewer process steps.

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"Batch Spray Processors: Reducing Cycle Time, Improving Performance," by Erik Olson (FSI) and Byron Palla (TI)

Abstract: Through rinse optimization, we have developed the FlashClean™ Advantage package for the ZETA^® Spray Cleaning System. As shown in our work and at Texas Instruments production facility, the FlashClean™ Advantage not only produces manufacturing advantages of reduced cycle time and chemical and water consumption but also improves particle performance for the 65nm technology node. The benefits are widely applicable to all spray applications.

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"Front End Processes," by Jeffrey Butterbaugh, FSI Internatinal; Larry Larson, SEMATECH and Texas Instruments; Raj Jammy, SEMATECH

Scope: The Front End Processes (FEP) chapter of the ITRS (International Technology Roadmap for Semiconductors) focuses on future process requirements and potential solutions for the continued scaling of devices based on field effect transistors (FET); including high-performance, lowoperating power and low-standby power logic devices; dynamic random access memory (DRAM) devices; and nonvolatile memory devices. This chapter defines comprehensive future requirements and potential solutions for the key front end wafer fabrication process technologies and materials associated with these devices. It addresses equipment and materials, as well as unit and integrated processes beginning with the substrate and extending through contact silicidation and deposition of strain layers. This chapter also addresses fabrication of storage nodes for the various memory devices.

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"Resist Removal and Cleaning for TANOS Metal Gate Nonvolatile Memories," by Enrico Bellandi, Cinzia De Marco, Numonyx and Antonio Truscello, Jeffery Butterbaugh, FSI, published in Future Fab, June 2009

Abstract: Advanced nonvolatile memory devices utilizing metal gate stacks are not compatible with standard plasma ashing and wet chemical processes for resist removal and cleaning. These standard processes cause metal oxidation and metal etching, which damage the device. A new wet chemical approach for resist removal and cleaning has been developed using hot, 150°C, H₂SO₄ with very low levels of H₂O₂ followed by diluted NH₄OH.

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“Selective Etching of High-k,” Solid State Technology Web Exclusive, July 2003

Abstract: The deposition of blanket films with a subsequent etch after gate patterning remains the leading candidate for integrating high-k gate dielectrics at the 70nm node. Early high-k material candidates such as BST etched easily in a range of acidic chemistries, but device and material studies have now converged on the oxides, nitrates, and silicates of Al, Zr, and Hf, and particularly on HfO₂ based compounds.

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"Steam-Injected SPM Process for All-Wet Stripping of Implanted Photoresist," by David DeKraker, Blake Pasker, Jeffrey Butterbaugh, Kurt Christenson and Thomas Wagener, FSI Internatinal

Introduction: Photoresist stripping in IC manufacturing has become more challenging as the number of photoresist levels has increased while at the same time allowable material loss and surface damage has decreased. Heavily implanted photoresist is especially challenging due to the dehydrogenated, amorphous carbon layer that forms on the surface [1]. To facilitate implanted photoresist removal, this layer can be attacked by physical processes such as ion bombardment as part of the common dry ashing approach. However, these physical approaches can lead to surface damage and increased material loss. Another approach is to increase the reactivity of the sulfuric acid – hydrogen peroxide mixture (SPM), so that it can penetrate and dissolve the amorphous carbon layer and achieve complete photoresist removal.

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“Strategies for Second-Hand Equipment in China,”

Abstract: While used equipment has been widely used in China and contributing to a strong advantage in low-cost manufacturing, the Chinese IC industry also needs technology upgrade to continue the rapid growth. Can 2nd hand equipment continue to be useful at the next nodes? We offer strategies and examples from our work with leading IC makers worldwide.

“The Litmus Test ’Selective Etching of High-k Dielectric Films’,” by Kurt Christenson, FSI, published in European Semiconductor, June 2005

“Wet Resist Strip Capability vs. Implant Energy,” by Kurt K. Christenson, FSI International, presented at the 212th ECS Meeting, October 2007

Abstract: Implant doses greater than 5E14 atoms/cm² can create an amorphous carbon like damage layer (crust) that is difficult to dissolve with wet chemistries. During the wet strip, the undamaged and lightly-damaged resist is dissolved quickly, undercutting and releasing most of the crust. The portions of crust that contact the silicon, however, cannot be undercut, and must be dissolved. The most extensive and difficult to dissolve regions of crust typically occur near the edge-bead-removal (EBR) region.

This work uses the SRIM (Stopping Range of Ions in Matter) computer simulation to investigate the characteristics of the crust for a range of implant conditions including dose, energy and implant species. Techniques to prevent the formation of attached crust near the edge bead region are also discussed.

"Advances on 45nm SiGe-Compatible NiPt Salicide Process," by Yi-Wei Chen, Nien-Ting Ho, Jerander Lai, T.C. Tsai, C.C. Huang, S.F. Tzou, UMC; and James Chu, FSI International

Introduction: NiPt self-aligned silicide (salicide) has become a major candidate for the 45nm node due to its better thermal stability and the surface morphology of NiSi on Si substrate [1,2]. SiGe has been proposed for PMOS strain engineering [3]. The relevant SiGe oxidation behavior [4], reaction with platinum [5] and thermal stress behavior [6] are important factors in developing a process for 45nm NiPt salicide over SiGe stressor. These concerns require the review of the current process for NiPt to verify its compatibility and extendibility.

"Front End Processes," by Jeffrey Butterbaugh, FSI Internatinal; Larry Larson, SEMATECH and Texas Instruments; Raj Jammy, SEMATECH

Scope: The Front End Processes (FEP) chapter of the ITRS (International Technology Roadmap for Semiconductors) focuses on future process requirements and potential solutions for the continued scaling of devices based on field effect transistors (FET); including high-performance, lowoperating power and low-standby power logic devices; dynamic random access memory (DRAM) devices; and nonvolatile memory devices. This chapter defines comprehensive future requirements and potential solutions for the key front end wafer fabrication process technologies and materials associated with these devices. It addresses equipment and materials, as well as unit and integrated processes beginning with the substrate and extending through contact silicidation and deposition of strain layers. This chapter also addresses fabrication of storage nodes for the various memory devices.

“High Temperature Control of Platinum,” by Bruno Imbert, Stephane Zoll, STMicroelectronics and Carols Morote, Jeffery Butterbaugh, FSI, published in euroasia semiconductor, Issue III 2009.

Abstract: Platinum is being used as an alloy with nickel to help control nickel salicide migration into silicon. Platinum is not easy to remove with traditional etchants creating a challenge for CMOS manufacturers. The authors discuss a potential solution.

“New Technologies in Immersion Cleaning,” by Weiping Ma, FSI International

Abstract: Although immersion cleaning has been a mature technology for wafer cleaning for many years, there are still advancements made today, especially targeted for 90nm and below technology nodes. In this column, we will introduce some of FSI International’s innovations in immersion cleaning.

“Selective Etching of High-k,” Solid State Technology Web Exclusive, July 2003

Abstract: The deposition of blanket films with a subsequent etch after gate patterning remains the leading candidate for integrating high-k gate dielectrics at the 70nm node. Early high-k material candidates such as BST etched easily in a range of acidic chemistries, but device and material studies have now converged on the oxides, nitrates, and silicates of Al, Zr, and Hf, and particularly on HfO₂ based compounds.

“Strategies for Second-Hand Equipment in China,”

Abstract: While used equipment has been widely used in China and contributing to a strong advantage in low-cost manufacturing, the Chinese IC industry also needs technology upgrade to continue the rapid growth. Can 2nd hand equipment continue to be useful at the next nodes? We offer strategies and examples from our work with leading IC makers worldwide.

“The Litmus Test ’Selective Etching of High-k Dielectric Films’,” by Kurt Christenson, FSI, published in European Semiconductor, June 2005

"Characterizing Etch Residue Removal for Batch Processing of Spin-On Low-k Dielectric Materials," Semiconductor Manufacturing, volume 4, issue 11, page 128, November 2003

Abstract: Spin-on low-k dielectric materials, including SiLK and MSQ, are being integrated into BEOL Cu interconnect structures. Post-etch residue removal must selectively dissolve the organometallics without attacking the low-k or Cu film. We demonstrate such a substrate-safe stripper, GenSolve 670, in a batch spray system. A complete cycle time of 30 minutes is possible, providing a throughput near 200 wph.

“Improved Post-etch Via Clean with Fluoride-based Semi-aqueous Chemistry using an Intermediate Rinse,” Cleaning Technology in Semiconductor Device Manufacturing VII, ECS Proceedings, volume 2001-26, pages 258-265, 2002

Abstract: An improved post-etch via cleaning process is studied using a fluoride-based semi-aqueous chemistry in a multi-position spray processing tool. The process uses two separate dispense steps of the semi-aqueous chemistry, with an intermediate deionized water rinse. Inclusion of the intermediate rinse significantly improves the removal of post etch residues. This improved cleaning is likely due to a diffusion process by which a layer of initial by-products is rinsed away by the intermediate rinse. The underlying contaminants are then exposed to the second chemical dispense step allowing complete removal. The combined time of the two separate chemical dispenses is much less than the time required for a single chemical dispense process.

“Non-Damaging Chemical Photoresist Strip Process for Copper Low-k Interconnects,” by Philip G. Clark and Kurt Christenson (FSI), presented at SEMI Advanced Semiconductor Manufacturing Conference 2005

“Non-Damaging Cleaning Processes for Porous Low-k Materials,” by Philip G. Clark and Darren L. Moore (LSI Logic)

Abstract: Photoresist removal using traditional plasma ash chemistries leads to severe degradation of low-k dielectric properties including increases in k-value and changes in critical dimensions. We present a new process using ozone-saturated, deionized water (DIO3) in a batch spray processor. This process yields no changes in the low-k dielectric properties or changes in critical dimensions, as shown on CVD organosilicate glass (OSG) low-k. In addition, we also demonstrate the use of corrosion inhibitors to reduce copper corrosion during the ozone process.

“Rapid and Controlled Stripping of Thick Resists for Semiconductor BEOL Applications”

“Reducing Time in Batch Cleaning,” by Jeffery Butterbaugh, FSI International

Abstract: Wafer cleaning represents up to 15% of the total process steps to build an advanced, 90-nm semiconductor device and is still mainly carried out in batch processes. Performance and throughput advantages are the main reasons for the persistence of batch processing in cleaning. However, concerns about cycle time are driving development of single wafer cleaning processes. Jeffery W. Butterbaugh of FSI International looks at alternatives for maintaining performance and throughput while realizing gains in productivity for cleaning processes.

"Suppression of Galvanic Corrosion in Advanced BEOL Integration," by Jeffrey W. Lauerhaas, FSI, published in Solid State Technology, September 2009

Executive Summary: A single wafer closed chamber system has been developed to control oxygen levels during processing. This control has enabled the use of hydrofl uoric acid for post etch cleans of advanced (32nm) BEOL processes. Without oxygen control, processing with hydrofl uoric acid is not possible due to excessive corrosion of the exposed materials.

“Using Cost-Effective Dilute-Acid Chemicals to Perform Postetch Interconnect Cleans,” by Hong-Seong Sohn, Samsung Electronics; and Jeffery W. Butterbaugh, Erik D. Olson, John Diedrick, and Nam-Pyo Lee, FSI International

“45nm Node Wafer Cleaning Techniques For Meeting the Challenges of Advanced Semiconductor Manufacturing,” by Jeffery Butterbaugh, FSI International and Charles Gould, Entegris, published in Semiconductor Manufacturing, May 2006

Abstract: On December 13, 2005, the most recent version of International Technology Roadmap for Semiconductors (ITRS) was introduced during a public conference in Seoul, Korea. From the presentations regarding semiconductor design and manufacturing, it is certain that the future of semiconductor manufacturing will continue to present significant challenges for both front-end-of-line (FEOL) and back-end-of-line (BEOL) surface preparation and critical cleaning steps. This article reviews some of the most pressing challenges facing end-users, process tool manufacturers and materials suppliers, challenges that must be addressed in order to meet the progression of the ITRS.

“Advanced Cryogenic Aerosol Cleaning: Application to Damage Free Cleaning of Sensitive Structured Wafers,” by Jeffery M. Lauerhaas, James F. Weygand and Greg P. Thomes, FSI, Proceedings: Advanced Semiconductor Manufacturing Conference 2005

“Cryogenic Aerosol for Zero-Damage Cleaning,” by Jeffrey Lauerhaas and Carlos Morote, FSI International, and Jean-Phillippe Plé, Altis, published in Semiconductor International, December 2005

“Enhancing Yield Through Argon/Nitrogen Cryokinetic Aerosol Cleaning After Via Processing,” by Jeffery W. Butterbaugh, Steve Loper and Greg Thomes, FSI International; and Dale Sheu, Texas Instruments, published in MICRO, June 1999

"FSI Applications Note (1211-ANS-0403)"

Abstract: The CryoKinetic technology provides a unique method for particle removal — all-dry, non-reactive, and brushless, customers find applications in many insertion points.

“Improved Yields for the Nano-Technology Era Using Cryogenic Aerosols,” by Thomas J. Wagener (FSI) and Kazushi Kawaguchi (Fujitsu), Proceedings: Advanced Semiconductor Manufacturing Conference, May, 2004

Abstract: This paper describes field usage of cryogenic aerosol processing on 180nm and 130nm devices. Significant advantages of this particle removal technology is demonstrated and discussed.

“Non-Damaging Particle Removal Using Cryogenic Aerosols,” by Thomas J. Wagener, James F. Weygand and Greg P. Thomes, FSI, presented at Seventh Annual UCPSS – September 20-22, 2004

“Particle Removal Challenges and Solutions for the Nano-Technology Era,” by Thomas J. Wagener and Jeffery W. Butterbaugh, FSI

Abstract: As the particle removal from wafer surfaces becomes more difficult at more advanced technology nodes, cryogenic aerosols are being adopted by an increasing number of IC makers. We elaborate on four aspects of the cryogenic aerosol process that are behind this trend – The does not alter the properties of exposed materials, is compatible with fragile structures, offers superior particle removal efficiency especially on hydrophobic surfaces, and has demonstrated increased final yields in production at 180nm and 130nm.

“Preparation, Characterization, and Damage-free Processing of Advanced Multiple-Gate FETs,” Jeffrey M. Lauerhaas, FSI International, Rinn Cleavelin and Weize Xiong, Texas Instruments, Koki Mochizuki, Kara Sherman, Hucheng Lee and Brian Clappin, KLA-Tencor and Thomas Schulz, Klaus Schruefer, Infineon Technologies, to be published in the proceedings of the 2006 UCPSS.

Introduction: Advanced transistor structures, such as the Multiple-Gate FET (MuGFET), offer improved shortchannel effects control compared to the bulk-Si MOSFET [1]. Hence they may be adopted in CMOS technology as early as the 32nm technology generation [2]. MuGFET current conduction is on the sidewalls of silicon fins. Thus tall fins are desirable for high drive current per unit footprint. At the same time, short channel effect (SCE) control requires narrow fin width. Therefore, for the 32nm technology generation, silicon fin width is expected to be ~15nm while silicon fin height will be ~50nm. Such tall and narrow features present unique challenges to front end cleaning and defect inspection, which must be addressed before MuGFETs can be introduced into a manufacturing environment. In this paper we present a silicon fin stability study to address these challenges. Currently available inspection and cleaning technologies in this work have demonstrated the ability to inspect with a high defect of interest capture rate and to clean the silicon fins without damage. Pre- and post-inspection indicate no damage to the silicon fins for each of the three cleaning technologies.

“Rinsing: A Critical Process in Particle Removal,” by Kurt Christenson

Abstract: Rinsing is a critical process in particle removal. This paper examines fundamental mechanisms of rinsing and applies these principles to the development of ramped rinsing in spray cleaning. Results include better particle removal and reduced water consumption.

“Using a Cryogenic Aerosol Process to Clean Copper, Low-k Materials Without Damage,” Micro, volume 20, number 2, page 23, February 2002

Abstract: Cryogenic aerosol of argon and nitrogen has been shown effective at particle removal and yield enhancement for interconnect fabrication. Cryogenic aerosol is particularly useful with copper and low-k dielectrics because it achieves efficient particle removal while avoiding many of the problems of traditional liquid chemical cleans. The cleaning efficiency of cryogenic aerosol has been demonstrated on polished surfaces and surfaces with open vias while having no effect on low-k films. Low-k, very low-k, and ultra low-k (porous) films have been investigated using FTIR and ellipsometry.

“Yield Improvement Using Cryogenic Aerosol for BEOL Defect Removal,” by Jeffrey M. Lauerhaas and Yav San Kok, FSI International; and Ameer Hamzah and Ling Tze Tan, Chartered Semiconductor Manfacturing Ltd., presented at the 212th ECS Meeting, October 2007

Abstract: A dry, cryogenic aerosol has been integrated into an advanced copper low k dielectric process flow for defect removal. The cryogenic aerosol is able to remove particulate defects from the exposed substrate materials without etching, charging or altering the conducting or insulating properties of the exposed materials. In this work, the cryogenic aerosol is composed of a mixture of argon and nitrogen. The results have confirmed high defect removal efficiency ultimately resulting in a yield increase. The application of a wet clean was not possible without adverse, yield decreasing side effects. Three BEOL processing steps will be covered in this work. The three steps are defect removal after via etch, film deposition, and in-line electrical probe.