OTS (February 2009) -- With the recent publication of the 2008 ITRS update, and papers given at the latest IEDM Conference [1-5] it is clear that the broader integrated circuit (IC) industry is boldly moving into the paradigm of high-k/metal gate (HKMG) logic devices. In addition, the ITRS indicates junction depths for source/drain extensions continue to decrease as gate length continues to scale. These two trends drive key surface preparation challenges.
The trend to shallower junctions has been a driver for more selective removal of implanted photoresist.[6] In the area of source/drain extension (SDE) implantation (also referred to as “lightly-doped-drain” or “LDD”) this need is especially critical. These implants are trending towards energies of less than 1keV, which places most of the dopant very near the surface of the silicon, within the top 20Å.[6] Even a few angstroms of silicon loss after implantation can result in significant dopant loss. This problem is compounded by the fact that today’s complex chips include a variety of transistor designs, all on the same chip each requiring a different set of implants. The shallow implanted dopant not only has to withstand the stripping of its own implant mask, but also the stripping of 6-10 additional implant masks. This situation is what drives the physically perplexing ITRS metric that each implant mask strip step for 32nm LDD implants must remove less than 0.3Å of silicon or silicon oxide – a fraction of the Si-Si or Si-O bond length (2.3Å and 1.6Å, respectively). Lower implant energy does make the implanted photoresist relatively easier to remove, so given the trend to lower LDD implant energy, all-wet photoresist strip processes meeting these strict material loss requirements are achievable with FSI ViPR™ technology.
However, the introduction of HKMG at 32nm has created a new challenge. If the spacer on the HKMG sidewall does not provide adequate coverage, it might be breached during LDD implant photoresist stripping processes. Some metal gate candidates, such as titanium nitride (TiN), are etched very quickly in sulfuric acid and hydrogen peroxide mix (SPM). If the sidewall spacer is breached or the spacer coverage is incomplete, the TiN can be etched away by SPM, resulting in device failure. A major challenge for 32nm LDD implanted photoresist stripping is to remove the photoresist with minimal silicon loss, minimal dopant loss, and no damage to the metal gate. While dry ashing can avoid damage to the metal gate, it may not be able to meet the silicon and dopant loss requirements. Today, FSI is working on new approaches to all-wet photoresist removal with metal gate compatibility.
In summary, IC manufacturing surface preparation processes are challenged by the introduction of new materials and the trend towards shallower implants. FSI will continue to work with the leading IC manufacturers to develop and test new hardware and chemical approaches to meet the challenge of these new paradigms.
References:
[1] “32nm Gate-First High-k/Metal-Gate Technology for High Performance Low Power Applications,” IEDM 2008 Proceedings, 629(2008).
[2] “32nm General Purpose Bulk CMOS Technology for High Performance Applications at Low Voltage,” IEDM 2008 Proceedings, 633(2008).
[3] “A 45nm Low Power System-On-Chip Technology with Dual Gate (Logic and I/O) High-k/Metal Gate Strained Silicon Transistors,” IEDM 2008 Proceedings, 637(2008).
[4] “A Cost-Conscious 32nm CMOS Platform Technology with Advanced Single Exposure Lithography and Gate-First Metal Gate/High-K Process,” IEDM 2008 Proceedings, 938(2008).
[5] “A 32nm Logic Technology Featuring 2nd-Generation High-k + Metal-Gate Transistors, Enhanced Channel Strain and 0.171μm2 SRAM Cell Size in a 291Mb Array,” IEDM 2008 Proceedings, 941(2008).
[6] “Material Loss Impact on Device Performance for 32nm CMOS And Beyond,” UCPSS 2008 Proceedings, Solid State Phenomona Vols. 145-146, 245(2009).
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