The MAGELLAN® Batch Immersion Cleaning System is designed to meet the challenges of advanced IC manufacturing by providing the lowest defectivity and most uniform processes of any immersion cleaning system on the market. The MAGELLAN® system combines FSI’s cleaning technology with innovative new advancements, all packaged in a modular, configurable design. MAGELLAN® is a true bridge platform that is available in 200mm or 300mm and can be modified in the field from one wafer size to the other.
Benefits
- Lowest defectivity
- Most uniform etching with FSI’s SymFlow® technology
- Minimized capital investment as a result of configurable and extendible design
- Field expandable with additional modules and flow streams
- Best-of-breed IPA rinse/dry method using FSI’s STG® technology
- High particle removal efficiency with shadow-free megasonics and proprietary rinsing techniques
News
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Yield improvement using the MAGELLAN® System’s flexibility to achieve recipe optimization
- FEOL Critical Clean and Etch
- FEOL Strip and Clean
- MOL Strip and Clean
- BEOL Strip and Clean
- Defect Removal
OTS (September 2008) -- In their FSI Knowledge Services™ Seminar presentation, Nirit Sofer and Lev Sherbelis of Numonyx confirmed significant yield gains in flash memory production after optimizing the SC1 cleaning process to increase particle removal efficiency (PRE), noting that the detailed optimization was enabled by the MAGELLAN® System’s flexible but precise recipe control of multiple process parameters (see Figure 1).
MoreFSI Receives U.S. Patent Strengthening Its Intellectual Property Portfolio for Surface Tension Gradient (STG®) Technology
OTS (February 2008) -- The U.S. Patent and Trademark Office has awarded FSI a patent for a method which improves rinsing and drying microelectronic devices in immersion tanks for front-end-of-line (FEOL) critical cleans. This patent further strengthens and broadens FSI’s patent portfolio in the area of surface tension gradient (STG®) rinse/dry process and provides IC makers with industry-leading rinse dry performance for 300mm FEOL critical cleaning at 65nm, 45nm, and future generations. The STG® process is currently used in the FSI MAGELLAN® immersion cleaning system.
MoreFirst High Throughput MAGELLAN® System Shipped for Production
OTS (July 2007) -- The first MAGELLAN® immersion cleaning system on the new high throughput platform has been shipped for use in several production applications at a major logic and memory manufacturer in the US. The MAGELLAN® system has seen widespread acceptance, with the number of installed systems doubling in the last two years. Currently tools are installed in all three major manufacturing regions, Asia, Europe and North America, in both logic and memory fabrication, and in 65nm production and 45nm development applications.
MoreFSI International Expands Its Technology Portfolio for Advanced High-k Gate Applications with Allowance of a New Patent
MINNEAPOLIS (June 26, 2007) -- FSI International, Inc. (Nasdaq: FSII) announced today that it received Notice of Allowance from the U.S. Patent and Trademark Office for a surface preparation method of forming an ultra-thin silicon oxide layer required prior to deposition of a high dielectric constant (high-k) film. This patent broadens FSI’s technology portfolio to further address the needs of IC manufacturers when implementing high-k technology in the fabrication of 45nm and 32nm devices.
MoreFSI International Receives U.S. Patent for Method of Combining Uniform Etching with Rinsing and Drying in a Single Immersion Tank
MINNEAPOLIS (May 16, 2007) -- FSI International, Inc. (Nasdaq: FSII) announced today that the U.S. Patent and Trademark Office has awarded the company a patent for a method which produces ultra-uniform etch results in combination with a rinse/dry step in a single immersion tank for front-end-of-line (FEOL) critical cleans. This advancement is part of FSI’s SymFlow™ technology and is integrated with FSI’s exclusive surface tension gradient (STG®) rinse/dry process for use in the MAGELLAN® Immersion Cleaning System.
MoreITRS Timing Adjustments Affect New Surface Preparation Requirements
OTS (February 2007)
MoreNew Hot Acid Cleaning Process Eliminates Etching and Damage Associated with SC1 and Megasonics
OTS (February 2007) -- FSI has developed a proprietary process for removing particles added by hot acid processes and avoids the unwanted etching and damage that can occur with conventional cleaning processes.
MoreIncreasing use of Silicon Nitride for IC Manufacturing Drives New Requirements for Wet Etching
OTS (November 2006) -- Jeffery W. Butterbaugh, FSI International Chief Technologist
While IC manufacturers continue to add new elements and materials to the production of advanced devices, they are also introducing variations and increasing the use of more standard materials like silicon nitride.
MorePre-treatment Suppresses Native Oxide Loss and Silicon Attack During Hot Phosphoric Acid Nitride Etch Process
OTS (November 2006) -- Using its MAGELLAN® Immersion Cleaning System, FSI has demonstrated the ability of proprietary pretreatment steps to suppress native oxide loss and silicon attack during nitride etch with hot phosphoric acid. Normally, hot phosphoric acid will quickly etch away the native oxide exposing the underlying silicon to attack.
MoreEnhanced MAGELLAN® Platform Offers World Class or HVM Throughput Up To 400 WPH
OTS (November 2006) -- FSI’s newly enhanced MAGELLAN® Immersion Cleaning System now offers throughput up to 400 WPH. Throughput enhancing improvements include a faster wafer handling robot and an optional dual robot configuration.
MoreFSI International Introduces New Silicon Nitride Selective Etch Processes using its MAGELLAN® Immersion Cleaning System
MINNEAPOLIS (November 14, 2006) -- FSI International, Inc. (Nasdaq: FSII) announced today new selective nitride etch processes that suppress oxide and silicon attack without generating high particle counts using its MAGELLAN® Immersion Cleaning System. These applications were developed and proven in the FSI laboratory on customer wafers as part of a 45nm advanced technology program. These applications will be useful for older technology generations as well.
MoreStrain Engineering for Mobility Enhancement Drives Wet Processing Challenges
OTS (July 2006) -- Strain engineering for mobility enhancement has become one of the most important transistor fabrication techniques for keeping our industry on the “Moore’s Law” curve during this current era of “Scaling by Innovation”.
MoreMAGELLAN® Immersion Cleaning System Nitride Etch Demonstrates Unrivaled Selectivity and Uniformity
OTS (July 2006)-- Nitride etch using the MAGELLAN® immersion cleaning system has demonstrated unrivaled selectivity and uniformity. In selectivity tests, the system has repeatedly removed up to 3,500Å of nitride with no measurable oxide loss. Uniformity within wafers averages 1.7 percent at one sigma for 300 mm wafers.
MoreFSI International Receives Multi-Unit Order for its MAGELLAN® Immersion Cleaning System from Leading U.S. IC Manufacturer
MINNEAPOLIS (June 6, 2006) — FSI International, Inc. (Nasdaq: FSII) today announced that a world-leading U.S. IC manufacturer has placed a multi-unit order for its 200/300mm MAGELLAN® Immersion Cleaning System. This order is a result of the MAGELLAN system’s best-of-breed particle and etch uniformity performance. The tools will be used in manufacturing and are expected to ship during the first half of FSI’s fiscal 2007.
MoreThe MAGELLAN® System Delivers Proven Process Performance for 65nm Technology
OTS (February 2006) -- The MAGELLAN® Immersion Cleaning System has been qualified for 65nm baseline manufacturing. Top chipmakers using the system have confirmed notable process performance. The tool's 65nm process performance is highlighted by one customer's results for an oxide removal and surface preparation process.
MoreFSI International Introduces New Cleaning Processes for Advanced Technology Nodes New Processes Meet Customer Needs Well Ahead of ITRS Schedule
MINNEAPOLIS (June 30, 2005) -- FSI International, Inc. (Nasdaq: FSII) today announced new cleaning processes to meet the needs of leading IC makers well ahead of the International Technology Roadmap for Semiconductors (ITRS) guidelines for material loss. The ITRS calls for a maximum material loss per cleaning cycle of 0.4 angstrom at the 45nm technology node, while semiconductor manufacturers indicate their requirements are closer to 0.1 angstrom.
MoreFSI International Awarded U.S. Patent on Method for Etching High-k Films for Advanced Technology Nodes
MINNEAPOLIS (Feb. 15, 2005) -- FSI International, Inc. (Nasdaq: FSII), a manufacturer of capital equipment for the microelectronics industry, today announced that the U.S. Patent and Trademark Office has awarded the company a patent for a new process to etch high dielectric constant (high-k) films with high selectivity. The new process, which will be used at the 45-nm node and below, enables wet etching of high-k films – something not possible with traditional dielectric wet etch techniques.
MorePublications
“Front End Processes”
By: Jeffery W. Butterbaugh, Larry Larson, Raj Jammy, FSI International
The Front End Processes (FEP) chapter of the ITRS (International Technology Roadmap for Semiconductors) focuses on future process requirements and potential solutions for the continued scaling of devices based on field effect transistors (FET); including high-performance, lowoperating power and low-standby power logic devices; dynamic random access memory (DRAM) devices; and nonvolatile memory devices.
Download PDF“Preparation, Characterization, and Damage-free Processing of Advanced Multiple-Gate FETs”
By: Jeffrey M. Lauerhaas, FSI International, Rinn Cleavelin and Weize Xiong, Texas Instruments, Koki Mochizuki, Kara Sherman, Hucheng Lee and Brian Clappin, KLA-Tencor and Thomas Schulz, Klaus Schruefer, Infineon Technologies
Advanced transistor structures, such as the Multiple-Gate FET (MuGFET), offer improved shortchannel effects control compared to the bulk-Si MOSFET [1]. Hence they may be adopted in CMOS technology as early as the 32nm technology generation [2]. MuGFET current conduction is on the sidewalls of silicon fins.
Download PDF“New Technologies in Immersion Cleaning”
By: Weiping Ma, FSI International
Although immersion cleaning has been a mature technology for wafer cleaning for many years, there are still advancements made today, especially targeted for 90nm and below technology nodes. In this column, we will introduce some of FSI International’s innovations in immersion cleaning.
Download English Version PDF Download Simplified Chinese Version PDF“45nm Node Wafer Cleaning Techniques For Meeting the Challenges of Advanced Semiconductor Manufacturing”
By: Jeffery Butterbaugh, FSI International and Charles Gould, Entegris
On December 13, 2005, the most recent version of International Technology Roadmap for Semiconductors (ITRS) was introduced during a public conference in Seoul, Korea. From the presentations regarding semiconductor design and manufacturing, it is certain that the future of semiconductor manufacturing will continue to present significant challenges for both front-end-of-line (FEOL) and back-end-of-line (BEOL) surface preparation and critical cleaning steps.
Download English Version PDF Download Simplified Chinese Version PDF"Reducing Time in Batch Cleaning"
By: Jeffrey Butterbaugh, FSI International
Wafer cleaning represents up to 15% of the total process steps to build an advanced, 90-nm semiconductor device and is still mainly carried out in batch processes. Performance and throughput advantages are the main reasons for the persistence of batch processing in cleaning. However, concerns about cycle time are driving development of single wafer cleaning processes. Jeffery W. Butterbaugh of FSI International looks at alternatives for maintaining performance and throughput while realizing gains in productivity for cleaning processes.
“Single-Tank Processing Demonstrates Immersion Batch Cleaning for 65nm IC's (Advanced Immersion Batch Cleaning Processes Using Advanced and Flexible Configurations)”
By: Jeffery W. Butterbaugh and Nam-Pyo Lee
Download English Version PDF Download Traditional Chinese Version PDF“Uniform Ultra-thin Oxide Growth for High-k Pre-clean”
By: Jeffery Butterbaugh
To continue the scaling of integrated circuits, the standard silicon oxide gate is being replaced with higher dielectric constant (high-k) materials, which must be deposited onto a substrate terminated with an ultra-thin oxide layer. We describe a novel combination of saturated oxide growth and uniform oxide etch as the final step of a pre-clean process for high-k gate dielectrics.
Download PDF"HF Based Cleaning Processes for Current Applications and New Materials in an Advanced Immersion Cleaning System"
By: Nampyo Lee
Dilute HF (DHF) “cleans” is the most widely used cleaning method in semiconductor processing. In 300mm manufacturing, DHF processes must be exceptionally controlled to avoid particle deposition from adjacent, closely spaced (5mm) wafers and to result in good thin oxide etch uniformity.
Download PDF"Minimizing Oxide Loss in Immersion SC1 Process"
By Jeff Butterbaugh, Steve Loper and Tom Wagener
As IC scaling continues to push the limits, device manufacturers need to be able to clean without etch and thereby maintain device structure integrity. We have studied particle removal efficiency as a function of several SC1/megasonics parameters at low oxide loss conditions.
Download PDF"Better Wet Bench Productivity through a New Method of Rinse Optimization"
Conventional wet chemistry processing in semiconductor manufacturing is virtually under attack to reduce chemical volumes, water consumption, system footprint, and overall cost; the needs are even more severe when you consider 300mm wafer processing. In developing new capability to meet these demands, a group of engineers have come up with a novel method of monitoring rinse efficiency. The method itself attacks conventional wisdom about rinse efficiency.
Download PDF"Better HF Etch Uniformity with Single-Tank Approach"
Immersion processing, a tried-and-true method for wafer cleaning, has been redesigned from the ground up for 100nm and future technology nodes, as stricter processing tolerances are required. A new batch, single-tank process can achieve excellent uniformity in critical dilute HF (DHF) etches, and provide the uniformity of a dual-tank process in a single-tank footprint. The symmetrical, continuous-flow process eliminates the need for a dedicated HF bath, leading to an even smaller footprint. In cases where SC1 or ozonated DI water steps precede the DHF step, an additional dedicated rinse bath can also be eliminated.
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