The ORION® system enables critical path cleaning capabilities for ultra shallow junctions, high-k metal gates and Cu/low-k metal capping layers at 32nm and below. The ORION® system’s ViPR™ technology can strip more photoresist implant levels than competing single wafer wet cleaning products while meeting the material loss requirements for 32nm and 22nm devices. ViPR™ technology also enables the implementation of low temperature nickel platinum silicidation of silicon germanium. In addition, the system’s O2 control with energized spray bar chemical delivery provides high contamination removal efficiency while controlling metal etching and galvanic corrosion for MOL and BEOL cleans.
Benefits
- Closed and contained cleaning environment
- Effectively excludes oxygen to control metal etching, eliminate galvanic corrosion and prevent watermark formation
- ViPR™ all-wet photoresist stripping technology strips the most implant levels while meeting 32 and 22nm material loss requirements.
- ViPR™ technology achieves a 70% reduction in time and cost for single wafer stripping of implanted photoresist
- ViPR™ technology based salicide strip enables higher Pt concentrations with SiGe compatibility
- Integrated spray technology with energetic dispense provides improved performance compared to a single point nozzle in an open chamber
- Better etch uniformity
- Lower chemical and water usage
- Superior defectivity without pattern damage
- Shorter process time
- Improved defect, polymer and photoresist removal in a controlled environment
- Energetic delivery of higher temperature (>200°C) chemical etching and stripping
- Improved personnel and tool safety due to fume & splashing containment
- ORION® system’s 3-dimensional cluster platform of stacked chambers surrounding a single robot enables the industry’s smallest 8 chamber cleaning system
News
Publications
“Steam-Injected SPM Process for All-Wet Stripping of Implanted Photoresist”
By: David DeKraker, Blake Pasker, Jeffery W. Butterbaugh, Kurt K. Christenson, Thomas J. Wagener, FSI International
Photoresist stripping in IC manufacturing has become more challenging as the number of photoresist levels has increased while at the same time allowable material loss and surface damage has decreased.
Download 2008 UCPSS Proceedings Version PDF Download Semiconductor International March 2009 Version PDF“Front End Processes”
By: Jeffery W. Butterbaugh, Larry Larson, Raj Jammy, FSI International
The Front End Processes (FEP) chapter of the ITRS (International Technology Roadmap for Semiconductors) focuses on future process requirements and potential solutions for the continued scaling of devices based on field effect transistors (FET); including high-performance, lowoperating power and low-standby power logic devices; dynamic random access memory (DRAM) devices; and nonvolatile memory devices.
Download PDF“Preparation, Characterization, and Damage-free Processing of Advanced Multiple-Gate FETs”
Jeffrey M. Lauerhaas, FSI International, Rinn Cleavelin and Weize Xiong, Texas Instruments, Koki Mochizuki, Kara Sherman, Hucheng Lee and Brian Clappin, KLA-Tencor and Thomas Schulz, Klaus Schruefer, Infineon Technologies
Advanced transistor structures, such as the Multiple-Gate FET (MuGFET), offer improved shortchannel effects control compared to the bulk-Si MOSFET [1]. Hence they may be adopted in CMOS technology as early as the 32nm technology generation [2]. MuGFET current conduction is on the sidewalls of silicon fins.
Download PDFApplications
- FEOL Critical Clean and Etch
- FEOL Strip and Clean
- MOL Strip and Clean
- BEOL Strip and Clean
- Defect Removal