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ORION® Single Wafer Cleaning Cluster

ORION® Single Wafer Cleaning Cluster

The ORION® system enables critical path cleaning capabilities for ultra shallow junctions, high-k metal gates and Cu/low-k metal capping layers at 32nm and below. The ORION® system’s ViPR™ technology can strip more photoresist implant levels than competing single wafer wet cleaning products while meeting the material loss requirements for 32nm and 22nm devices. ViPR™ technology also enables the implementation of low temperature nickel platinum silicidation of silicon germanium. In addition, the system’s O2 control with energized spray bar chemical delivery provides high contamination removal efficiency while controlling metal etching and galvanic corrosion for MOL and BEOL cleans.

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Benefits

  • Closed and contained cleaning environment
    • Effectively excludes oxygen to control metal etching, eliminate galvanic corrosion and prevent watermark formation
    • ViPR™ all-wet photoresist stripping technology strips the most implant levels while meeting 32 and 22nm material loss requirements.
    • ViPR™ technology achieves a 70% reduction in time and cost for single wafer stripping of implanted photoresist
    • ViPR™ technology based salicide strip enables higher Pt concentrations with SiGe compatibility
  • Integrated spray technology with energetic dispense provides improved performance compared to a single point nozzle in an open chamber
    • Better etch uniformity
    • Lower chemical and water usage
    • Superior defectivity without pattern damage
    • Shorter process time
    • Improved defect, polymer and photoresist removal in a controlled environment
    • Energetic delivery of higher temperature (>200°C) chemical etching and stripping
    • Improved personnel and tool safety due to fume & splashing containment
  • ORION® system’s 3-dimensional cluster platform of stacked chambers surrounding a single robot enables the industry’s smallest 8 chamber cleaning system

News

    IC Industry Moving to Paradigm of High-k/Metal Gates and Shallower Junctions

    OTS (February 2009) -- With the recent publication of the 2008 ITRS update, and papers given at the latest IEDM Conference [1-5] it is clear that the broader integrated circuit (IC) industry is boldly moving into the paradigm of high-k/metal gate (HKMG) logic devices. In addition, the ITRS indicates junction depths for source/drain extensions continue to decrease as gate length continues to scale. These two trends drive key surface preparation challenges.

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    FSI’s NEW ORION® Single Wafer Cleaning System Officially Takes Off

    OTS (February 2009) -- On November 3, 2008, FSI officially entered the single wafer wet cleaning market with the ORION® System. In recent years IC manufacturers have been asking FSI for single wafer cleaning solutions -- FSI responded with the ORION® system. The ORION® system with its differentiated solutions is already providing unique critical path capabilities required for advanced technology nodes as reflected by orders received shortly after its launch.

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    FSI International Receives Follow-on Order for ORION® Single Wafer Cleaning Technology from Major Semiconductor Manufacturer

    New cleaning capability will be integrated into manufacturing for BEOL copper/low-k interconnect fabrication

    MINNEAPOLIS (January 7, 2009) — FSI International, Inc. (Nasdaq: FSII) a leading supplier of wafer processing, cleaning and surface conditioning equipment for semiconductor manufacturing, announced today the receipt of an additional order for its new ORION® single wafer cleaning technology from a major semiconductor manufacturer.

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    FSI International Receives Order for ORION® Single Wafer Cleaning System from Major Semiconductor Manufacturer

    Order represents acceptance of new single wafer cleaning technology for 32nm applications

    MINNEAPOLIS (December 23, 2008) — FSI International, Inc. (Nasdaq: FSII) a leading supplier of wafer processing, cleaning and surface conditioning equipment for semiconductor manufacturing, announced today the receipt of an order for its new ORION® single wafer cleaning platform from a major semiconductor manufacturer.

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    FSI International Releases ORION® Single Wafer Cleaning System

    Innovative closed-chamber design enables critical path cleaning capabilities for ultra shallow junctions, high-k/metal gates and metal capping layers at 32nm and below.

    MINNEAPOLIS (November 3, 2008) — FSI International, Inc. (Nasdaq: FSII) a leading supplier of wafer processing, cleaning and surface conditioning equipment for semiconductor manufacturing, announced today the release of its new ORION® Single Wafer Cleaning System.

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    FSI Ships Single Wafer Cleaning Technology Selected by a Major Semiconductor Manufacturer for Development of 32nm BEOL Cleaning Processes

    MINNEAPOLIS (May 13, 2008) -- FSI International, Inc. (Nasdaq: FSII), a leading manufacturer of wafer cleaning systems used in the fabrication of integrated circuits, announced today that it shipped its single wafer wet cleaning technology to a major semiconductor manufacturer for the development of back-end-of-line (BEOL) cleaning capability for 32nm IC manufacturing. After a thorough review of competitive alternatives, this customer determined that FSI’s technology best met its anticipated new requirements for 32nm device manufacturing. For the development program, FSI has shipped an evaluation ORION™ Single Wafer Cleaning Cluster.

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Publications

“Steam-Injected SPM Process for All-Wet Stripping of Implanted Photoresist”

By: David DeKraker, Blake Pasker, Jeffery W. Butterbaugh, Kurt K. Christenson, Thomas J. Wagener, FSI International

Photoresist stripping in IC manufacturing has become more challenging as the number of photoresist levels has increased while at the same time allowable material loss and surface damage has decreased.

Download 2008 UCPSS Proceedings Version PDF Download Semiconductor International March 2009 Version PDF

“Front End Processes”

By: Jeffery W. Butterbaugh, Larry Larson, Raj Jammy, FSI International

The Front End Processes (FEP) chapter of the ITRS (International Technology Roadmap for Semiconductors) focuses on future process requirements and potential solutions for the continued scaling of devices based on field effect transistors (FET); including high-performance, lowoperating power and low-standby power logic devices; dynamic random access memory (DRAM) devices; and nonvolatile memory devices.

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“Preparation, Characterization, and Damage-free Processing of Advanced Multiple-Gate FETs”

Jeffrey M. Lauerhaas, FSI International, Rinn Cleavelin and Weize Xiong, Texas Instruments, Koki Mochizuki, Kara Sherman, Hucheng Lee and Brian Clappin, KLA-Tencor and Thomas Schulz, Klaus Schruefer, Infineon Technologies

Advanced transistor structures, such as the Multiple-Gate FET (MuGFET), offer improved shortchannel effects control compared to the bulk-Si MOSFET [1]. Hence they may be adopted in CMOS technology as early as the 32nm technology generation [2]. MuGFET current conduction is on the sidewalls of silicon fins.

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Applications

  • FEOL Critical Clean and Etch
  • FEOL Strip and Clean
  • MOL Strip and Clean
  • BEOL Strip and Clean
  • Defect Removal