OTS (February 2006) -- Jeffery W. Butterbaugh, FSI International Chief Technologist

Over the past few years, a large portion of the research and development in cleaning processes has focused on achieving high-efficiency particle removal while minimizing damage and material loss.

(The material-loss goals of this effort are defined by Table 68 in the FEP Chapter of the 2005 ITRS found at http://index.phplic.itrs.net.) Material-loss goals are defined for individual cleaning steps at each technology generation, and provide a 0.5 Å allowance for the 65nm generation and a 0.3Å allowance for the 45nm generation.

While development efforts have focused mainly on meeting these numbers and maximizing particle removal, the real goal of IC manufacturers is an integrated process sequence that minimizes the amount of silicon lost in the source/drain regions next to the gate electrode. The amount of Si removed in these regions depends not only on the cleaning process, but also on the ashing and implantation steps. Ashing and implantation cause surface damage and oxidation, which lead to higher material loss during the cleaning step. The total source/drain silicon loss on completed 90nm generation chips can be measured at 90 – 130 angstroms (based on cross-sections published by Dick James, Chipworks, Inc., at the 2005 ASMC meeting). Proceedings available at IEEE.

An integrated approach to controlling material loss during the fabrication process (i.e., optimizing several steps together instead of individually) has a higher probability of maximizing overall cleaning efficiency and final yield while also minimizing material loss and physical damage. One integration solution currently under investigation uses a wet process to achieve the complete removal of implanted photoresist, thus eliminating the ashing step.

FSI has significantly improved the ability of the sulfuric acid – hydrogen peroxide process (also known as “piranha” or “Caro's”) to strip highly implanted photoresist. This allows for the elimination of the ashing step on most implant masks, and results in a much lower overall silicon loss. Details of this new development will be presented at the SEMICON Korea SEMI Technology Symposium Session S5 “Contamination-Free Manufacturing Technology” on February 9, 2006. The complete manuscript of that presentation will be available in the next issue of On The Surface e-Newsletter.

Understanding and optimizing the complete resist removal process sequence can result in better overall performance, as well as lower cost and lower cycle time. FSI will continue to use this approach as we address other IC manufacturing challenges.