OTS (February 2007)

Jeffery W. Butterbaugh, FSI International Chief Technologist

The recently released 2006 update to the International Technology Roadmap for Semiconductors, indicates a push out in the introduction to manufacturing of some key scaling items, such as advanced high-k/metal gate stacks and porous low-k materials, even though the roadmap for critical dimensions (“nodes”) remains unchanged. The concept of “More than Moore” is now firmly entrenched in the ITRS and it shows how the semiconductor industry will continue to add value, not just through traditional geometric and equivalent scaling (“Moore’s Law”), but also through added, non-digital functionality (Analog/RF, passives, sensors) on the chip and enhanced multichip packaging approaches like system-in-package (“SIP”). What does this mean for Surface Preparation?

In 2006, the FEP and PIDS Technology Working Groups of the ITRS reached agreement that advanced high-k/metal gate materials are not quite ready for manufacturing introduction. Pushout of advanced gates on the ITRS roadmap from 2008 to 2010 was enabled by the rapid adoption of strain engineering for channel mobility enhancement. However, recent announcements by Intel and IBM have indicated their plans to implement advanced high-k/metal gate materials on the original timeline. In addition, Sematech also announced that their advanced high-k/metal gate stack is ready for manufacturing integration. Details of these new advanced gate stacks have not been published, so it is still unknown exactly which materials will be used and their impact on surface preparation requirements are unclear.

While the need for new surface preparation processes for high-k and metal gate materials may have been pushed back on the ITRS, the integration of strain engineering has added other surface preparation needs. One of these needs is highly selective silicon nitride etching. In addition, scaling requirements continue to put pressure on achieving low resistance source/drain contacts with ultra-shallow junctions. The trend in shallower junctions continues to drive the requirements for resist stripping and cleaning processes that minimize surface damage, material loss, and dopant loss, such as ash-free resist stripping processes.

In the area of interconnect, the ITRS 2006 update recognizes that adoption of porous low-k materials (k<2.6) in manufacturing is being delayed. For instance the target bulk dielectric constant for MPU/ASIC devices in the years 2007 and 2008 has been changed from “k= 2.4” to “2.3-2.7”. This recognizes that there will be different implementations, with many manufacturers staying with dense, non-porous films. Porosity in inter-metal dielectric films creates many integration challenges, including cleaning and rinsing without degrading the film properties. While new approaches to cleaning and sealing porous materials are under development, their need in the manufacturing environment is being delayed in parallel with the implementation of porous films.

Increased integration of new functionality on chips, “More than Moore,” also creates some new cleaning challenges. The fabrication of passive devices on top of the chip, or of filters and lenses for imaging applications, is introducing materials that are not compatible with traditional cleaning methods. In some cases, non-chemical cleaning processes, such as cryogenic aerosol cleaning will be needed.

In summary, even though the ITRS 2006 update has indicated a few delays for technology implementations, the unending drive toward higher device performance continues to require new integration schemes and new materials which, in turn drive new surface preparation requirements.

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