OTS (February 2008) -- In the latest generation ZETA^® system, the new ViPR™ process now offers two recipe types ViPR™ and ViPR™+. The new ViPR™ technology further improves the established ViPR™ process by optimizing conditions to achieve the highest stripping levels with the lowest possible material loss. This is critical for both Logic and DRAM manufacturers.

The ViPR™ recipe is used as the foundation to ashless resist stripping where it provides extremely low oxide or silicon material loss (<1 Å) while delivering excellent strip performance. This process is capable of stripping implants up to 5e14@10keV, which includes most LDD type implants. Some LDD and most S/D implants require the more aggressive ViPR™+ strip process. This process is capable of ashless stripping up to 5e15 @10keV with a slightly higher oxide or silicon material loss. Compared to the traditional ash and wet strip method where material loss can range over 10 Å per strip step, the ViPR™ process truly enables a low material loss method of resist stripping.

Figure 1. The ZETA^® system ViPR™ process reduces material losses during photoresist stripping by 50% compared to ash and wet clean processes as noted by this customer data.

The new ViPR™ technology also increases productivity and reduces cost. With on-wafer temperatures exceeding 200°C, the system can achieve the desired strip and material loss performance in a significantly shorter process. Shortening the process has the dual benefit of reducing chemical consumption (up to 40% less) and improving process throughput (more than 30%). As a result of these latest improvements the ZETA^® system ViPR™ process remains the most cost effective method of accomplishing ashless resist stripping with the lowest low material loss.

For more information on FSI ViPR™ technology for ashless photoresist stripping, please click here.