OTS (Novemeber 2006) -- AMD’s Fab 36 presented the results of their evaluation of FSI’s ANTARES^® aerosol cleaning process used to recover yield after electrical in-line testing. The results demonstrated the process’s ability to remove nearly all debris generated by testing, allowing engineers to return tested wafers to production.

This conclusion not only allows the recovery of yield previously sacrificed to gain valuable parametric data, but also alters the cost benefit calculation for in-line testing in favor of additional testing to permit better process characterization and control.

Traditionally, device manufacturers have been faced with a decision between testing at first metal (in-line testing) to measure the electrical performance of transistors formed by FEOL processing, or waiting until the conclusion of wafer processing to test finished devices. In-line testing results in the sacrifice of a significant number of die, or often the entire wafer, due to defects generated by the testing process. On the other hand, waiting until the completion of wafer processing potentially risks all work-in-progress (WIP) between defect creation and detection. As BEOL processing has become more elaborate, with some designs having eleven or more metal layers, the cost, the time required, and the value of WIP have made this risk of delayed testing unacceptable, and manufacturers have chosen to regard the yield loss associated with in-line testing as an economically acceptable cost. The cost is significant. Typical sampling strategies sacrifice one wafer per lot, or 1000 wafers per month for a fab with 25,000 wafers starts.

Electrical testing generates defects because it requires physical contact between a probe and the circuit, usually a bond pad or, in the case of in-line testing, a test structure located in the scribe lines between die. The contact creates a scrub mark and often sheds material from the test structure. If this material finds its way to the active circuitry it can create shorts between lines, or between the current layer and subsequent metal layers. Conventional cleaning processes cannot be used to remove the test debris since they incorporate corrosive oxidizing chemistries that are incompatible with exposed copper found in advanced logic devices. ANTARES^® Cryokinetic Cleaning System uses dry, inert argon and nitrogen gases that are completely compatible with copper. The process directs a high velocity gas jet at the wafer surface where frozen gas clusters dislodge contaminating debris that is then caught up and removed by the flowing gas.

The AMD study looked specifically at in-line testing at the first metal layer in a copper process. Debris related defects were detected by electrical testing at the next metal layer. Figure 1 shows a wafer map of defects before and after cleaning. It includes micrographs of several defects. Figure 2 maps several wafers in the test lot. Circles indicate wafers that were not cleaned and red squares mark defects. Clearly, the defects correlate strongly with the uncleaned wafers. Figure 3 charts the functional yield improvements of approximately 19% that AMD attributed to the cleaning process on two different lots that received 100% testing for reticle qualification.

Figure 1: Defect maps before and after ANTARES^® CX cryogenic aerosol treatment indicating the types of defects that are easily removed.

Figure 2: Yield maps for 100% probed wafers showing yield loss on wafers that did not receive ANTARES^® CX cryogenic aerosol treatment. The ANTARES^® CX process virtually eliminates probe yield loss.

Figure 3: Final yield of wafers that were 100% probed for reticle qual. Final yield improved by 19% for wafers that received the ANTARES^® CX cryogenic aerosol treatment.

This study demonstrates the very high particle removal efficiency (PRE) of the ANTARES^® CryoKinetic cleaning system process for this type of physically attached defect. The process allows manufactures to recover nearly all of the yield loss associated with in-line electrical test. Equally important, it virtually eliminates the yield penalty associated with in-line testing, encouraging additional testing for better process characterization and tighter process control.

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