“Steam-Injected SPM Process for All-Wet Stripping of Implanted Photoresist”

By: David DeKraker, Blake Pasker, Jeffery W. Butterbaugh, Kurt K. Christenson, Thomas J. Wagener, FSI International

Photoresist stripping in IC manufacturing has become more challenging as the number of photoresist levels has increased while at the same time allowable material loss and surface damage has decreased.

“Front End Processes”

By: Jeffery W. Butterbaugh, Larry Larson, Raj Jammy, FSI International

The Front End Processes (FEP) chapter of the ITRS (International Technology Roadmap for Semiconductors) focuses on future process requirements and potential solutions for the continued scaling of devices based on field effect transistors (FET); including high-performance, lowoperating power and low-standby power logic devices; dynamic random access memory (DRAM) devices; and nonvolatile memory devices.

“Wet Resist Strip Capability vs. Implant Energy”

By: Kurt K. Christenson, FSI International

Implant doses greater than 5E14 atoms/cm² can create an amorphous carbon like damage layer (crust) that is difficult to dissolve with wet chemistries.

“All Wet Stripping of Implanted Photoresist”

By: Kurt K. Christenson, Jeffery W. Butterbaugh, Thomas J. Wagener, Nam Pyo Lee, Brent Schwab, Michael Fussy, John Diedrick, FSI International

A new all-wet piranha-based process capable of reaching 200°C on-wafer temperatures has been demonstrated for stripping implanted photoresist.

“A High-Temperature Batch-Spray Process for Implanted Resist Stripping”

By: Jeffery Butterbaugh, Kurt Christenson and Nam Pyo Lee

Photoresist stripping in IC manufacturing has become more challenging as the number of photoresist levels has increased, while at the same time allowable material loss and surface damage has decreased. Heavily implanted photoresist is especially challenging due to the dehydrogentated, amorphous carbon layer that forms on the surface.

“45nm Node Wafer Cleaning Techniques For Meeting the Challenges of Advanced Semiconductor Manufacturing”

By: Jeffery Butterbaugh, FSI International and Charles Gould, Entegris

On December 13, 2005, the most recent version of International Technology Roadmap for Semiconductors (ITRS) was introduced during a public conference in Seoul, Korea. From the presentations regarding semiconductor design and manufacturing, it is certain that the future of semiconductor manufacturing will continue to present significant challenges for both front-end-of-line (FEOL) and back-end-of-line (BEOL) surface preparation and critical cleaning steps.

“The Litmus Test ’Selective Etching of High-k Dielectric Films’”

By: Kurt Christenson

"Strategies for Second-Hand Equipment in China"

While used equipment has been widely used in China and contributing to a strong advantage in low-cost manufacturing, the Chinese IC industry also needs technology upgrade to continue the rapid growth. Can 2nd hand equipment continue to be useful at the next nodes? We offer strategies and examples from our work with leading IC makers worldwide.

"Batch Spray Processors: Reducing Cycle Time, Improving Performance"

By: Erik Olson
Through rinse optimization, we have developed the FlashClean™ Advantage package for the ZETA^® Spray Cleaning System. As shown in our work and at Texas Instruments production facility, the FlashClean™ Advantage not only produces manufacturing advantages of reduced cycle time and chemical and water consumption but also improves particle performance for the 65nm technology node. The benefits are widely applicable to all spray applications.

“Selective Etching of High-k”

Solid State Technology Web Exclusive

The deposition of blanket films with a subsequent etch after gate patterning remains the leading candidate for integrating high-k gate dielectrics at the 70nm node.

“An Integrated Wet Chemical Etch-Strip-Clean Sequence,” Solid State Technology

An investigation was conducted to determine the source of a yield-limiting defect identified on all product types at a wafer fab. The defect was isolated to patterning operations in the frontend section of the device process where a conventional multistep sequence was used. The problem was traced to a wet chemical buffered oxide etching step and attributed to drying wafers before ashing the resist film.